Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

Yu, Xinhai; Chai, Changchun; Xingrong, Ren; Yang, Yong; Xi, Xiaowen; Yang, Liting

doi:10.1088/1674-4926/35/8/084011

Cited by 10 publications

(9 citation statements)

References 13 publications

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“…As expected, raising the temperature increases the delay (above 30 °C for DICE) due to the lower electrical conductivity (lower carrier's mobility) and increases the power consumption (above 60 °C for DICE), as high temperature increases current leakage [33]. However, the temperature effect on the proposed D-latch is lower than in other D-latches, such as LSEH-1, DICE, and TPDICE-based D-latches, as deduced from Figure 10 (a comparative study in terms of a temperature coefficient has been included in Appendix A).…”

Section: Temperature Variationsupporting

confidence: 61%

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

et al. 2021

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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Section: Temperature Variationsupporting

confidence: 61%

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

et al. 2021

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“…In a previous paper, we established a two-dimensional (2D) simulation model of a CMOS inverter and indicated that the latch-up effects induced by HPM are ambient temperature dependent [6]. In this paper, using the simulation model, we validate the analytical models and interpret the HPM upset susceptibility as a function of frequency.…”

Section: Introductionmentioning

confidence: 83%

“…As analyzed in [6], latch-up easily forms in CMOS inverter under the HPM action. Once latch-up forms, high current density causes a large amount of heat, resulting in the temperature within the device increasing continuously.…”

Section: Influence Of the Excess Carrier Effectmentioning

confidence: 99%

“…Second, the electromagnetic environment becomes more complex due to either unintentional change such as the more complicated implementations of circuitry like radio frequency (RF) etc. or intentional electromagnetic interference (EMI) [3][4][5][6][7]. In high-power electromagnetic environments, high-power microwaves will be easily coupled to ICs of the electronic systems, causing latch-up thereby resulting in interference, permanent malfunction, and even physical damage of systems [3].…”

Section: Introductionmentioning

confidence: 99%

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Modeling and understanding of the frequency dependent HPM upset susceptibility of the CMOS inverter

Chai

Liu

et al. 2015

Sci. China Inf. Sci.

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In this paper, we interpret and, for the first time, model a frequency dependent high-power microwave (HPM) upset susceptibility. We constructed the analytical models of the total amount of injected charges N inj , the excess carrier density distribution in P-Substrate, and the frequency dependent HPM upset susceptibility level. The models are validated by simulated results and experimental data, respectively. Results reveal that N inj is proportional to f α while the exponent α should be adjusted to −0.525. The excess carrier density distribution behaves the frequency dependence as well; the dependence is attributable to the fact that the AC field within the CMOS inverter varies too rapidly for the carriers to follow at high frequency. Meanwhile, the HPM upset susceptibility level is a decreasing function of f . The f dependent HPM upset susceptibility model is verified to be reliable and able to quickly estimate the susceptibility level of CMOS inverter considering IC technology, layout parameters, pulse properties, and operating environment simultaneously. Besides, the empirical formula P = A · f α is proposed to provide instant estimation to the HPM upset power threshold. In conclusion, by aid of the analytical model, we acquired the influence of the layout parameter L B on the HPM susceptibility and demonstrated that the CMOS inverter with minor L B is more susceptible to HPM.

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“…theoretically revealed the influences of some HPM parameters on the performance of CMOS inverter [16,17]. Yu et al analytically discussed and deduced the effects of HPM frequency, HPM pulse-width and temperature on CMOS inverter by analyzing fundamental physical parame-ters [18,19,20]. For other types of circuits and devices, Ma et al and Chai et al explained the failure mechanism induced by HPM of bipolar transistor and proposed several protective measures [21,22,23,24,25].…”

Section: Introductionmentioning

confidence: 99%

Upset and damage mechanisms of the three-dimensional silicon device induced by high power microwave interference

Chai

Liu

et al. 2019

IEICE Electron. Express

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The paper clearly reveals the mechanism of upset (bit error) and damage caused by high power microwave (HPM) interference for the three-dimensional silicon device. The 0.35 µm process related three-dimensional model of two stages cascaded CMOS inverters is established for the first time utilizing semiconductor device simulator Sentaurus-TCAD to comprehendingly study the HPM interference mechanism. Moreover, a detailed mechanism about the upset induced by HPM interference is performed. Furthermore, the process and mechanism of damage generated by HPM interference are explored by using this model. The dependences of the damage power threshold P and damage energy threshold E on the pulsewidth τ are both in negative exponential relationship. The simulation results in this paper have a good coincidence with the experimental results.

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Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

Cited by 10 publications

References 13 publications

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Modeling and understanding of the frequency dependent HPM upset susceptibility of the CMOS inverter

Upset and damage mechanisms of the three-dimensional silicon device induced by high power microwave interference

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