The redox kinetics of VO 2? /VO 2 ? and V 3? / V 2? couples on a carbon paper (CP, HCP030 N, Shanghai Hesen, Ltd., China) electrode were investigated in terms of their standard rate constant (k 0 ) and reaction mechanism. The values determined for k 0 for VO 2? ? VO 2 ? and V 3? ? V 2? using the CP electrode are 1.0 9 10 -3 and 1.1 9 10 -3 cm s -1 , respectively. The value of k 0 increases by one or two order(s) of magnitude compared with values obtained using electrodes composed of pyrolytic graphite and glassy carbon. The acceleration of the redox kinetics of vanadium ions is a result of the large surface area of the CP electrode. An inner-sphere mechanism for the reaction on the surface of the electrode is proposed. The kinetic features of vanadium redox reactions on the CP electrode reveal that CP is suitable for use as the electrodes in vanadium redox-flow batteries.

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A 12-channel 120Gb/s laser diode driver array has been designed in 0.18μm CMOS technology. Under a supply voltage of 1.8V, simulated results show that a single channel has a speed of 10Gb/s at a power consumption of 98mW. A total capacity of 120 Gb/s can be obtained from 12 channels. With three stages of differential amplifiers directly coupled, the single channel amplifier can supply the current up to 26mA adopting negative feedback and capacitive coupled current amplifier (C 3 A) structure. The adjustable modulation current from 1mA to 16mA and the bias current up to 10mA can be generated from this driver circuit. The layout area of the driver array is 3205μm×506μm. This design can be used in high speed optical chips. Keywords-laser diode driver array; 12 channels; C 3 A; active negative feedbackI.

A 6-bit low power current steering data to analog converter (DAC) which sampling frequency up to 8GHz is presented. The converter consists of 4MSBs and 2LSBs, trading off between the precision and complexity of circuit. The 8-GSample/s conversion rate has been obtained by fully custom designed thermometer decoder and synchronization circuit. The spurious free dynamic rang (SFDR) more than 34.2 dB has been obtained from dc to 2.7GHz at sampling frequency of 8GHz. The power consumption at an 8GHz sampling frequency for a near Nyquist sinusoidal output signal equals 15.7mW. The DAC occupies 0.485 mm × 0.675 mm in a 65nm CMOS technology.