An 8GS/s 6-bit current steering DAC in 65nm CMOS technology

Xiong, Wu; Li, Wenyuan; Sun, Changyin

doi:10.1109/atc.2014.7043438

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“…In the modern ultra-wide-band wireless communication system, the digital-analog converter (DAC) is critical in signal processing. In high speed communication system, medium resolution DAC with high sampling rate is also used extensively [1][2][3]. As the development of the modern communication system, the performance of the DAC has become one of the most important bottlenecks.…”

Section: Introductionmentioning

confidence: 99%

A 10GS/s 8-bit Current Steering DAC in 65nm CMOS Technology

2017

Proceedings of 2017 the 7th International Workshop on Computer Science and Engineering

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A 10GS/s 8-bit low power current steering DAC in TSMC 65nm CMOS technology is presented.An ingenious way to minimize the mismatch is introduced by mirroring and shifting the current source cells. Also, a switch driver which generates high-cross point and low-swing driving waveform is used in the DAC. It increases the static and dynamic performance of the DAC. The converter adopts the segmented thermometer decoder consisting 4MSBs and 4LSBs, trading off between the complexity and the power. The spurious free dynamic range (SFDR) up to 43dB has been simulated over the entire Nyquist bandwidth at 10GS/s. The total power consumption is 37.5mW at 10GS/s. The DAC occupies an area of 0.7mm × 0.85mm.

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Section: Introductionmentioning

confidence: 99%