This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm(2) of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations.

Index Terms-Analog-to-digital converters, brain-machine interfaces, digitally programmable, energy efficient, low power, neural amplifiers, neural-recording systems.

Abstract-This paper presents work on ultra-low-power circuits for brain-machine interfaces with applications for paralysis prosthetics, stroke, Parkinson's disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode-recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented.

Abstract-This paper presents work on ultra-low-power circuits for brain-machine interfaces with applications for paralysis prosthetics, stroke, Parkinson's disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode-recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented.

The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain– machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than . We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.

Abstract-Algorithmically and energetically efficient computational architectures that operate in real time are essential for clinically useful neural prosthetic devices. Such devices decode raw neural data to obtain direct control signals for external devices. They can also perform data compression and vastly reduce the bandwidth and consequently power expended in wireless transmission of raw data from implantable brain-machine interfaces. We describe a biomimetic algorithm and micropower analog circuit architecture for decoding neural cell ensemble signals. The decoding algorithm implements a continuous-time artificial neural network, using a bank of adaptive linear filters with kernels that emulate synaptic dynamics. The filters transform neural signal inputs into control-parameter outputs, and can be tuned automatically in an on-line learning process. We provide experimental validation of our system using neural data from thalamic head-direction cells in an awake behaving rat.

Frequency compensation of a multistage operational amplifier (op-amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op-amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two-stage and three-stage op-amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well-known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed-loop poles and zeros of the op-amp. Intuitive graphical design procedures for two-stage and three-stage op-amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three-stage op-amp in a standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) process. With a load capacitance of 500 pF, post-layout simulations show that the op-amp achieves a low-frequency gain of 144 dB, a phase margin of 58 ∘ , and a unity-gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8-V supply voltage. Comparisons with the published amplifiers show that our op-amp achieves the figure of merits comparable to those of the state of the art. outer feedback path between the output nodes of the third and the first gain stages, NMC utilizes 'Miller effect' to split the poles associated with the two high-impedance nodes twice. Because of the presence of right-half-plane (RHP) zeros, the bandwidth limitation, and the high power required to achieve stability in NMC, other NMC-based compensation schemes have been proposed [9][10][11][12][13][14][15][16]. These techniques employ nulling resistors, active feedback, and feedforward transconductance to eliminate the RHP zeros, extend the unity-gain bandwidth, and enhance slew rate of the op-amp. To further extend the bandwidth without extra power consumption, reversed nested-Miller frequency compensation (RNMC) [5,[17][18][19][20][21][22] has been proposed. Instead of forming the inner feedback path between the output nodes of the third and the second gain stages, the inner feedback path is formed between the output nodes of the second and the first gain stages. As will be explained later in this paper, compared with the conventional NMC scheme, this choice of the inner feedback path allows for a higher unity-gain bandwidth in the forward-path transfer function before forming the outer loop. As a result, the overall op-amp can achieve a higher unity-gain bandwidth. When the active feedback technique is used to remove the RHP zeros such as in [18][19][20][21], RNMC is sometimes called reversed active-feedback frequency compensation (RAFFC). Because RAFFC allows for a high unity-gain bandwidth without extra passive resistors, it is the most efficient in terms of power consumption and chip area, thus will be the focus of this paper. Analyses of R...

Summary We present the design of a low‐power high open‐loop gain opamp for use in chopper‐stabilized capacitively coupled instrumentation amplifiers (CCIAs). The opamp utilizes the current‐reuse folded‐cascode topology and a low‐power gain‐boosting technique to maximize its power efficiency and open‐loop gain. The proposed technique is applied to the designs of two CCIAs: the conservative CCIA with a moderate current scaling ratio and the stringent CCIA with a very high current scaling ratio. Utilizing the current scaling ratio of 4:1, the conservative CCIA, designed and fabricated in a 0.18 μm CMOS process, consumes a total current of 1.69 μA from a 0.8‐V supply voltage and achieves a thermal noise floor of 56.5 nV/ Hz. Utilizing the current scaling ratio of 38:1, the stringent CCIA, designed and simulated in a 0.13 μm CMOS process, consumes a total current of 1.4 μA and achieves a thermal noise floor of 48 nV/ Hz. The proposed design technique should benefit the designs of low‐power instrumentation amplifiers in advanced processes in which channel‐length modulation and the limited current consumption and supply voltage make the designs of high open‐loop gain opamps difficult. Copyright © 2017 John Wiley & Sons, Ltd.