Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow added functionality to existing marks within the current mark area, such as monitoring process asymmetry or multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning. With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window is enhanced, while improved on-product overlay performance is obtained.
MEMS manufacturing in general and the litho step in particular could benefit tremendously from an enhanced focus range of waferstepper alignment systems. This would help the MEMS community to cope with large substrate topography or extreme thick resist films. In this study the performance range over which of the alignment system of an ASML PAS5000/50 system operates has been investigated.A test device that requires bulk micro machining was designed and processed. The required front to backwafer alignment (FTBA) was performed on alignment markers in cavities etched through a 100mm wafer. On the test device the FTBA overlay was measured electrically as well as optically using the metrology capability of the stepper alignment system. The results obtained demonstrate the capabilities of an existing alignment system to deal with high topographies. The overlay errors observed were dominated by the bulk micro machining processing.
A novel front-to-back alignment method, which does not require additional alignment sensors, is being developed for optical projection lithography tools. The system is designed such that it can be easily retrofitted to existing systems. By embedding a pair of tiny optics into the wafer stage, the existing Through-The-Lens (TTL) and/or Off-Axis (OA) alignment systems can be utilized, thereby avoiding the added complexity of supplementary alignment electronics and hardware. The front-to-back alignment is accomplished by imaging the alignment marks on the wafer back surface to the front and then using the standard front-side alignment system. To calibrate the front-to-back alignment module and to minimize the alignment errors, new metrology software is introduced. The front-to-back alignment accuracy is specified to be 500 nm (3 a), which provides typically twice the improvement compared to current state-of-the-art implementations. The front-to-back alignment capability is being developed in response to the requirements of the MEMS/MOEMS market.
The increased demand for high throughput lithography with Front to Back Alignment (FTBA) capability has led ASML to develop the FTBA functionality within its current platform. This option is named 3DAlign™ and aims at an FTBA overlay of 500 nm. To relate a position on the back side of a substrate to its front side, two back-side marks are projected from the back to the front side by two optical branches. In this way, the images of the back-side marks have the proper orientation and magnification to be aligned by the standard ASML alignment hardware. The metrology challenge is to calculate the back-side mark positions in front-side (exposure) coordinates and to compensate for the systematic errors introduced by the optical branches. An absolute relation between the front-and back-side positions on the substrate is obtained by calibrating the system with a special 3DAlign calibration wafer. This is a wafer that has marks on both sides with a known offset. In this paper, the basic ideas and algorithms for the FTBA metrology are discussed.
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