The porous nature of carbon nanotube (CNT) arrays allows for the unique opportunity to tailor their mechanical response by the infiltration and deposition of nano-scale conformal coatings. Here, we fabricate novel photo-lithographically defined CNT pillars that are conformally coated with amorphous silicon carbide (a-SiC) to strengthen the interlocking of individual CNTs at junctions using low pressure chemical vapour deposition (LPCVD). We further quantify the mechanical response by performing flat-punch nanoindentation measurements on coated CNT pillars with various high-aspect-ratios. We discovered new mechanical failure modes of coated CNT pillars, such as "bamboo" and brittle-like composite rupture as coating thickness increases. Furthermore, a significant increase in strength and modulus is achieved. For CNT pillars with high aspect ratio (1:10) and coating thickness of 21.4 nm, the compressive strength increases by an order of magnitude of 3, towards 1.8 GPa (from below 1 MPa for uncoated CNT pillars) and the elastic modulus increases towards 125 GPa. These results show that our coated CNT pillars, which can serve as vertical interconnects and 3D super-capacitors, can be transformed into robust high-aspectratio 3D-micro architectures with semiconductor device compatible processes.

In this paper we report a novel transfer-free graphene fabrication process, which does not damage the graphene layer. Uniform graphene layers on 4" silicon wafers were deposited by chemical vapor deposition using the CMOS compatible Mo catalyst. Removal of the Mo layer after graphene deposition results in a transfer-free and controlled placement of the graphene on the underlying SiO 2 . Moreover, pre-patterning the Mo layer allows customizable graphene geometries to be directly obtained, something that has never been achieved before. This process is extremely suitable for the large-scale fabrication of MEMS/NEMS sensors, especially those benefitting from specific properties of graphene, such as gas sensing.

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As a first assessment for the fabrication of Geiger mode avalanche photodiode arrays, single pixel devices have been made. A CMOS compatible technology is used to allow the future integration of pixels in an array with readout electronics. A model for afterpulsing is presented that relates the afterpulsing probability to the concentration and capture cross section of the traps in the depletion layer. The bias voltage and temperature dependence of the dark count rate is explained by a trap assisted tunneling model. Measured results on fabricated devices are compared with theory.

Abstract-A novel silicon-on-glass integrated bipolar technology is presented. The transfer to glass is performed by gluing and subsequent removal of the bulk silicon to a buried oxide layer. Low-ohmic collector contacts are processed on the back-wafer by implantation and dopant activation by excimer laser annealing. The improved electrical isolation with reduced collector-base capacitance, collector resistance and substrate capacitance, also provide an extremely good thermal isolation. The devices are electrothermally characterized in relationship to different heat-spreader designs by electrical measurement and nematic liquid crystal imaging. Accurate values of the temperature at thermal breakdown and thermal resistance are extracted from current-controlled Gummel plot measurements.