We propose a p-MoS2/HfS2 van der Waals (vdW) heterostructure tunneling field-effect transistor (TFET) with a type-II band alignment for future power-efficient electronics. The differences in temperature dependence between p-MoS2/HfS2 TFET and HfS2 metal-oxide-semiconductor field-effect transistor showed that the turn-on current of p-MoS2/HfS2 TFET originated from band-to-band tunneling. To suppress the impact of interface traps, reduce the subthreshold swing (SS), and increase the gate capacitance, the 25 nm Al2O3 gate dielectric was replaced with a 15 nm HfO2 layer. Additionally, a buried Ni back-gate structure was introduced to reduce the area of overlap between the gate, contact electrodes, and gate leakage along with the scaling of equivalent oxide thickness. Subsequently, enlargement of gate capacitance by three times led to the reduction of SS from 700 to 300 mV dec−1, which verified that increasing the gate capacitance suppressed the impact of interface traps and improved gate controllability in the vdW heterostructure TFET.
In this study, we fabricated a p-MoS2/HfS2 van der Waals heterostructure tunneling FET (TFET), converting the bottom layers of the HfS2 channel into a HfOx insulator for a superior semiconductor/insulator interface using UV-O3 treatment. The TFET exhibited a long steep-slope region with a subthreshold swing (SS) of approximately 100 mV dec−1 over three decades of channel current, along with a minimum SS of 95 mV dec−1. We also implemented a low-temperature measurement and observed a clear negative differential resistance below 150 K, which could be strong evidence of band-to-band tunneling.
This work details a study based on HfS2 transistors utilizing an n-octadecylphosphonic acid-based self-assembled monolayer (SAM) as the gate dielectric. The fabrication of the SAM-based two-dimensional (2D) material transistor is simple and can be used to improve the quality of the interface of air-sensitive 2D materials. In comparison to HfS2 transistors utilizing a conventional Al2O3 gate insulator by atomic layer deposition, HfS2 transistors utilizing an SAM as the gate dielectric can reduce the operation region from 4V to 2V, enhance the field-effect mobility from 0.03 cm2/Vs to 0.75 cm2/Vs, improve the sub-threshold swing from 404 mV/dec to 156 mV/dec, and optimize the hysteresis to 0.03 V, thus demonstrating improved quality of the semiconductor/insulator interface.
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