p-MoS&lt;sub&gt;2&lt;/sub&gt;/HfS&lt;sub&gt;2&lt;/sub&gt; van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO&lt;sub&gt;2&lt;/sub&gt; Dielectric

Zhang, Wenlun; Netsu, Seiko; Kanazawa, Tamotsu; Amemiya, Tomohiro; Miyamoto, Y.

doi:10.7567/ssdm.2018.m-7-04

Cited by 1 publication

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“…We demonstrated the p-MoS 2 /HfS 2 vdW TFET and how the gate dielectric affected its performance. 23,24) In this paper, we would like to summarize and give a systematic illustration of the p-MoS 2 /HfS 2 vdW TFET with solutions to recent challenges to improve the performance.…”

Section: Introductionmentioning

confidence: 99%

Effect of increasing gate capacitance on the performance of a p-MoS₂/HfS₂ van der Waals heterostructure tunneling field-effect transistor

Zhang

Netsu

Kanazawa

et al. 2019

Jpn. J. Appl. Phys.

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We propose a p-MoS2/HfS2 van der Waals (vdW) heterostructure tunneling field-effect transistor (TFET) with a type-II band alignment for future power-efficient electronics. The differences in temperature dependence between p-MoS2/HfS2 TFET and HfS2 metal-oxide-semiconductor field-effect transistor showed that the turn-on current of p-MoS2/HfS2 TFET originated from band-to-band tunneling. To suppress the impact of interface traps, reduce the subthreshold swing (SS), and increase the gate capacitance, the 25 nm Al2O3 gate dielectric was replaced with a 15 nm HfO2 layer. Additionally, a buried Ni back-gate structure was introduced to reduce the area of overlap between the gate, contact electrodes, and gate leakage along with the scaling of equivalent oxide thickness. Subsequently, enlargement of gate capacitance by three times led to the reduction of SS from 700 to 300 mV dec−1, which verified that increasing the gate capacitance suppressed the impact of interface traps and improved gate controllability in the vdW heterostructure TFET.

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Section: Introductionmentioning

confidence: 99%

Effect of increasing gate capacitance on the performance of a p-MoS₂/HfS₂ van der Waals heterostructure tunneling field-effect transistor

Zhang

Netsu

Kanazawa

et al. 2019

Jpn. J. Appl. Phys.

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p-MoS<sub>2</sub>/HfS<sub>2</sub> van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO<sub>2</sub> Dielectric

Cited by 1 publication

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Effect of increasing gate capacitance on the performance of a p-MoS₂/HfS₂ van der Waals heterostructure tunneling field-effect transistor

Effect of increasing gate capacitance on the performance of a p-MoS₂/HfS₂ van der Waals heterostructure tunneling field-effect transistor

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p-MoS<sub>2</sub>/HfS<sub>2</sub> van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO<sub>2</sub> Dielectric

Cited by 1 publication

References 0 publications

Effect of increasing gate capacitance on the performance of a p-MoS2/HfS2 van der Waals heterostructure tunneling field-effect transistor

Effect of increasing gate capacitance on the performance of a p-MoS2/HfS2 van der Waals heterostructure tunneling field-effect transistor

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Effect of increasing gate capacitance on the performance of a p-MoS₂/HfS₂ van der Waals heterostructure tunneling field-effect transistor

Effect of increasing gate capacitance on the performance of a p-MoS₂/HfS₂ van der Waals heterostructure tunneling field-effect transistor