Carbon nanotubes (CNTs) are promising candidates for smart electronic devices. However, it is challenging to mediate their bandgap or chirality from a vapor-liquid-solid growth process. Here, we demonstrate rate-selected semiconducting CNT arrays based on interlocking between the atomic assembly rate and bandgap of CNTs. Rate analysis confirms the Schulz-Flory distribution which leads to various decay rates as length increases in metallic and semiconducting CNTs. Quantitatively, a nearly ten-fold faster decay rate of metallic CNTs leads to a spontaneous purification of the predicted 99.9999% semiconducting CNTs at a length of 154 mm, and the longest CNT can be 650 mm through an optimized reactor. Transistors fabricated on them deliver a high current of 14 μA μm−1 with on/off ratio around 108 and mobility over 4000 cm2 V−1 s−1. Our rate-selected strategy offers more freedom to control the CNT purity in-situ and offers a robust methodology to synthesize perfectly assembled nanotubes over a long scale.

Power dissipation is a fundamental issue for future chip-based electronics. As promising channel materials, two-dimensional semiconductors show excellent capabilities of scaling dimensions and reducing off-state currents. However, field-effect transistors based on two-dimensional materials are still confronted with the fundamental thermionic limitation of the subthreshold swing of 60 mV decade−1 at room temperature. Here, we present an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary threshold switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV decade−1 subthreshold swing (over five decades). This is achieved by using the negative differential resistance effect from the threshold switch to induce an internal voltage amplification across the MoS2 channel. Notably, in such devices, the simultaneous achievement of efficient electrostatics, very small sub-thermionic subthreshold swings, and ultralow leakage currents, would be highly desirable for next-generation energy-efficient integrated circuits and ultralow-power applications.

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Synaptic transistors mimicking the biological synapse's short term plasticity and short-term memory property were demonstrated using the amorphous indium-gallium-zinc oxide channel in combination with the nanogranular SiO 2 as the gate oxide. The lowest energy consumption was ∼1.08 pJ per pulse activity and the operating voltage was within 100 mV. The device's plasticity and memory characteristics can be explained by the movement of protons in the insulating layer. The proton relaxation was revealed by two ways of dual sweeping: continuous and discontinuous sweepings. We observed that the excitatory postsynaptic current (EPSC) rose as the voltage decreased anomaly during the backward sweeping process. In the electrical stimulus, both the short-term potentiation and depression were observed for this proposed device. The amplitude of the EPSC changed with the pulse number following a saturating exponential function. For the electrical stimulus under constant illumination, the UV light wavelength, intensity and duration time were found to have little effect on the paired pulse facilitation. While in the light stimulus, the light frequency promoted the paired pulse facilitation and had more effect on the synapse's plasticity than the other light pulse parameters including intensity, numbers and width. INDEX TERMS Synaptic transistor, transparent oxide, IGZO, nanogranular SiO 2 , UV light.

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In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40µA/µm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressedat the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decadewas obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application. INDEX TERMS TFET Ge PAI, line tunneling, cryogenic temperature.

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