Atomic threshold-switching enabled MoS2 transistors towards ultralow-power electronics

Abstract

Power dissipation is a fundamental issue for future chip-based electronics. As promising channel materials, two-dimensional semiconductors show excellent capabilities of scaling dimensions and reducing off-state currents. However, field-effect transistors based on two-dimensional materials are still confronted with the fundamental thermionic limitation of the subthreshold swing of 60 mV decade−1 at room temperature. Here, we present an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary threshold switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV decade−1 subthreshold swing (over five decades). This is achieved by using the negative differential resistance effect from the threshold switch to induce an internal voltage amplification across the MoS2 channel. Notably, in such devices, the simultaneous achievement of efficient electrostatics, very small sub-thermionic subthreshold swings, and ultralow leakage currents, would be highly desirable for next-generation energy-efficient integrated circuits and ultralow-power applications.

A Review on MoS2 Properties, Synthesis, Sensing Applications and Challenges

“…A Sulfur treatment with Alcohol is performed to enhance the contact resistance of MoS 2 FETs of gate lengths (500 to 80 nm) to be 1.3 kΩ [75]. An enhancement in the on/off switching characteristics and subthreshold swing (SS) of MoS 2 FET using Ag is presented in [76], where the device has SS ~4.5 mm/decade with less leakage and steep on/off characteristics. MoS 2 monolayer is used in nonvolatile memory applications [77], with high charge storage capacity.…”

Ultra‐Steep‐Slope High‐Gain MoS2 Transistors with Atomic Threshold‐Switching Gate

“…The performance comparison among the steep‐slope transistors is shown in Figure 3c,d . Compared with other classical low SS prototype devices, including TFETs, [ 16 , 17 , 18 , 19 , 20 ] impact‐ionization FETs (IMOS‐FETs), [ 21 ] Dirac‐source FETs (DS‐FET), [ 8 , 9 ] phase‐transition FET (phase‐FETs), [ 22 , 23 ] resistive‐switching FETs (TS‐FETs), [ 10 , 24 , 25 ] NC‐FETs, [ 26 , 27 , 28 ] nano‐electro‐mechanical FETs (NEM‐FETs), [ 29 ] RG‐FETs, [ 11 , 12 ] this work presents extremely steep SS below 1 mV dec −1 and high switching ratio of 2.76 × 10 7 , indicating MoS 2 RG‐FETs are promising for high‐performance low‐power electronics.…”

“… Statistical data of the MoS 2 RG‐FETs. a) The cycle‐to‐cycle variations of forward sweeping SS and reverse sweeping SS at V DS = 0.1 V. b) The device‐to‐device deviations of forward sweeping SS and reverse sweeping SS at V DS = 0.1 V. c,d) SS and I ON comparisons of various steep‐slope FETs, respectively, including TFETs, [ 16 , 17 , 18 , 19 , 20 ] impact‐ionization FETs (IMOS‐FETs), [ 21 ] Dirac‐source FETs (DS‐FET), [ 8 , 9 ] phase‐transition FET (phase‐FETs), [ 22 , 23 ] resistive‐switching FETs (TS‐FETs), [ 10 , 24 , 25 ] NC‐FETs, [ 26 , 27 , 28 ] nano‐electro‐mechanical FETs (NEM‐FETs), [ 29 ] RG‐FETs, [ 11 , 12 ] and this work. …”

“…However, due to the series connection of the memristor and transistor, high drive voltage and low on‐state output current are needed. [ 10 , 11 , 12 ]…”

Polarization‐Induced Band‐Alignment Transition and Nonvolatile p‐n Junctions in 2D Van der Waals Heterostructures

“…The atom-scale thickness and the absence of surface dangling bonds enable them significant advantage for the electrostatic control and van der Waals (vdW) integration, which is essential for the realization of functional devices with scaling dimensions and ultralow off-state power consumption. [5,6] The formation of p-n junctions is a fundamental step for the realization of 2D semiconductor devices used in transistors, memories, photodetectors, solar cells, and light-emitting diodes. [7,8] The doping via the intentional introduction of charged impurities into a semiconductor host lattice is the most common way to create excessive electrons or holes for the realization of p-n junctions.…”