In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bitinterleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-μW active power consumption.Index Terms-Bit-interleaving scheme, iso-area analysis, subthreshold static random-access memory (SRAM).
This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.
In this paper, an all digital push-pull linear voltage regulator is proposed that consists of a digital error detector, a voltage divider, a mode indicator, a pull device, and grouped push devices. The digital regulator is suitable for super-to near-threshold region operation by providing a variable output voltage that ranges from 0.5 to 1 V in steps of 0.1 V. The maximum load current is 100 mA for every output level. The current efficiency is 99.8% with only 164.5 A quiescent current on UMC 65-nm standard CMOS technology. A response time constraint is developed to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance and the size of the decoupling capacitor. A time interleaving control technique is then proposed to have a tradeoff between output performance, quiescent current, and the size of decoupling capacitor.
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