Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

Chang, Ming-Feng; Chiu, Yi-Te; Hwang, Wei

doi:10.1109/tcsii.2012.2198984

Cited by 70 publications

(27 citation statements)

References 11 publications

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“…The presented work shows a efficiently reduced area per bitcell (including peripheral circuits), compared to previous work, which use a full-custom storage cell integrated in an SCM [9], [10]. Furthermore, the area is competitive area with a recently presented 9T bitcell sub-V T SRAM, [6]. Moreover, the memory in this work is only 2× larger than the one in [5], although, compared to large sub-V T SRAMs, [4] there is still a large gap.…”

Section: B Silicon Measurementsmentioning

confidence: 84%

“…Another popular approach is to use fullcustom SRAMs with larger bitcells, 8-14 transistors (8T-14T), together with read-and write-assist techniques to operate in the weak inversion region. Correct operation deep down in the sub-V T region using this approach has been demonstrated by various authors, [2]- [6], and even at smaller technology nodes, [7], [8]. A third approach uses standard-cell based memories (SCMs) as previously demonstrated in [9], [10].…”

Section: Introductionmentioning

confidence: 85%

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A 35 fJ/bit-access sub-V<inf>T</inf> memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

Andersson

Mohammadi

Meinerzhagen

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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A 128× × ×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standardcell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32 % is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-VT VT VT), down to 370 mV, and data is retained down to 320 mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation. I. INTRODUCTIONIn recent years, the interest for ultra-low power (ULP) systems has increased rapidly, often achieved by aggressive supply voltage (V DD ) scaling deep down into the subthreshold (sub-V T ) region [1]. To accommodate ULP systems with memories, several approaches have emerged. A straightforward approach is to use commercial SRAMs with bitcells constructed from 6 transistors (6T) operated in a separate power domain with a higher V DD , and use level shifters to communicate with the ULP domains. Another popular approach is to use fullcustom SRAMs with larger bitcells, 8-14 transistors (8T-14T), together with read-and write-assist techniques to operate in the weak inversion region. Correct operation deep down in the sub-V T region using this approach has been demonstrated by various authors, [2]-[6], and even at smaller technology nodes, [7], [8]. A third approach uses standard-cell based memories (SCMs) as previously demonstrated in [9], [10].The selection of the most suitable technique involves tradeoffs between area, energy, and operating frequency. In an ULPsystem, energy is often the most important constraint. A 6T-bitcell SRAM solution is in many cases most area efficient and has the highest memory bandwidth, but suffers from higher energy dissipation as operation is performed at a higher V DD . Furthermore, extra level shifters are required, which increase energy dissipation as well as system complexity. A 8-14T weak-inversion SRAM looses in area and bandwidth compared to a 6T SRAM, but is more energy efficient, and thus, a suitable candidate. In terms of engineering effort, a design with a complex floorplan which has many small and distributed memory blocks might benefit from an SCM approach. An SCM uses standard-cells to construct a memory that is synthesized together with the RTL code of the whole system, and is placed as "glue logic" close to, or even with the processing block. This gives flexibility to the ASIC designer,

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Section: B Silicon Measurementsmentioning

confidence: 84%

Section: Introductionmentioning

confidence: 85%

A 35 fJ/bit-access sub-V<inf>T</inf> memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

Andersson

Mohammadi

Meinerzhagen

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

View full text Add to dashboard Cite

show abstract

“…In order to obtain higher noise margin along with better performance, modification in cell topologies are done. Various 7T, 8T and 9T single ended and differential SRAM cells have been introduced to meet the future SRAM requirements at the cost of area [16][17][18][19][20]. In addition to this, subthreshold mode of operation is introduced to accomplish low power design criteria, where the devices operate at below threshold voltage [2].…”

Section: Bit-cell Designmentioning

confidence: 99%

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Yadav

Jain

Pattanaik

et al. 2015

Microelectronics Reliability

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“…In addition, the standby power increases because the 8T SRAM cell uses an additional RBL for the read operation. Both 10T [7] and 9T [8] SRAM cells have been designed to improve the RSNM by resolving the row half-select issue using vertical and horizontal word-lines (WLs). Thus, there is no dynamic power overhead caused by write-back operations.…”

Section: Introductionmentioning

confidence: 99%

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Yang

Jeong

Song

et al. 2016

IEEE Trans. Circuits Syst. I

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Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the halfselect issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper "1" writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area.Index Terms-FinFET, low-power design, near-threshold operation, single bit-line structure, SRAM cell. 1549-8328

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Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

Cited by 70 publications

References 11 publications

A 35 fJ/bit-access sub-V<inf>T</inf> memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

A 35 fJ/bit-access sub-V<inf>T</inf> memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

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