A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Yadav, Nandakishor; Jain, S.; Pattanaik, Manisha; Sharma, Govind

doi:10.1016/j.microrel.2015.05.014

Cited by 3 publications

(2 citation statements)

References 35 publications

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“…Among all the DG device structures [1] , Fin-FET has drawn significant interest in the semiconductor industry because of its quasi-planar structure and scalability than other planar DG structures [2] . FinFET showed the intensity of VLSI research that it can be scaled up to the shortest channel length for the given gate oxide thickness [3] . The undoped underlap region facilitates to reduce SCEs and leakage current.…”

Section: Introductionmentioning

confidence: 99%

“…The undoped underlap region facilitates to reduce SCEs and leakage current. It also reduces random dopant effects, which improves process variation effects [4] . These facilities are granted at the cost of increased source/drain (S/D) series resistance (R S/D ) that degrades the current driving capabilities and reliability [5] of the device.…”

Section: Introductionmentioning

confidence: 99%

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Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET

et al. 2018

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We propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (Gm) and subthreshold slope (SS). The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance. We analysed the variation in drive current for different values of carbon (C) mole fraction y in Si1−yCy. It is found that the mole fraction also helps to improve device lifetime, performance enhancement also pointed by transconductance variation with the gate length. All the simulations are performed in the 3-D Sentaurus TCAD tool. The proposed device structure achieved ION = 2.17 mA/μm for Si0.3C0.7 and found that Si0.5C0.5 is more suitable for the perspective of a process variation effect for 14 nm as the gate length. We introduce reliability issues and their solutions for Si1−yCy FinFET for the first time.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%