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The pyramid structure fabricated with the potassium hydroxide (KOH) anisotropically etched (100) silicon substrate has been deposited with a copper film as the bottom electrode of the programmable metallization cell (PMC) memory to significantly improve the resistive switching characteristic. As compared with the conventional flat copper electrode, this pyramid-structured electrode exhibited the set/reset voltage as low as 1/0.6 V and superior endurance of 2400 cycles at the set/reset voltages of −5/+3 V for the voltages pulsewidth of 1 µs. The high performance of this PMC could be attributed to high local electrical fields at the tips of the pyramid structure, resulting in the formation of the narrower conductive filaments that facilitate the lower operation voltage and better endurance.Index Terms-Potassium hydroxide (KOH) surface texturing, programmable metallization cell (PMC), pyramid structure, resistive random-access memory (RRAM or ReRAM).

The oxygen-plasma-functionalized carbon nanotube thin films on the flexible substrates as the pH sensing membranes of extended-gate field-effect transistors are proposed for the first time. The carbon nanotubes are ultrasonically sprayed onto the polyimide substrates followed by an oxygen-plasma functionalization. Such oxygen-plasma-treated carbon nanotube thin films (CNTFs) exhibit superior pH sensing characteristics with the sensitivity of 55.7 mV/pH and voltage linearity of 0.9996 in a wide sensing range of pH 1-13. Moreover, the excellent flexibility of carbon nanotube is also demonstrated and the oxygen-plasma-treated CNTFs still maintain the sensitivity of 53.6 mV/pH and voltage linearity of 0.9943 even after five-cycle bending test. These results reveal that the oxygen-plasma-treated CNTFs have great potentials in the practically disposal and wearable biosensor applications.Index Terms-Biosensors, carbon nanotube (CNT), extendedgate field-effect transistors (EGFETs), flexible substrates.

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Two new systolic architectures are presented for multiplications in the ®nite ®eld GF(2 m). These two architectures are based on the standard basis representation. In Architecture-I, the authors attempt to speed up the operation by using a new partitioning scheme for the basic cell in a straightforward systolic architecture to shorten the clock cycle period. In Architecture-II, they eliminate the one clock cycle gap between iterations by pairing off the cells of Architecture-I. They compare their architectures with previously proposed systolic architectures and a semisystolic architecture, and show that their Architecture-I offers the highest speed and Architecture-II the lowest hardware complexity.