Market drivers, technology scaling and integration trends of application processor packaging are first presented. Component level and board level quality and reliability challenges are then discussed in the areas of thin die and thin core package warpage, lead free flip chip die to package interconnect mechanical integrity, and lead free package to motherboard solder joint reliability. Challenges from package qualification methodology and use condition are also addressed.
Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. Many EDA companies have made great strides on developing primary design tools(such as circuit/interconnect tools), but the tool capabilities to build in reliability into design have not been addressed or have been developed in a reactive manner at best. DIR project has been started this year in order to spearhead the effort to remove DIR tool development barriers under SEMATECH's reliability thrust. SEMATECH's DIR project is made up of an industry team of DIR and CAD tool experts. Team's primary goals are to develop tool requirement and to enable EDA industry to develop the DIR tools in order to rapidly close the capability gaps. In this paper, DIR project goals and updates will be presented along with the prioritized tool gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-byconstruction such as reliability-constraint placeand-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover high-level tool requirements on top five prioritized tool requirements will be presented. In addition, maturity matrix on DIR tool capabilities will be presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects will be presented. Finally, strategies for communicating the tool requirements and dealing with future gaps will be discussed.
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