Abstract-A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N-epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2210 12 #=cm 2 at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4 2 10 10 #=cm 2 in the buried oxide.
Wepresent a methodology for thermal resistance RrH extraction from the Early voltage dependence on collector current. This method does not require pulsed, temperature, or frequency measurements and hence, can be easily automated:' Results for a BJT from an SOUDTI Complementay BiCMOS process and for a SiCe HBT from a 5OGHz BiCMOS process are presented and comparison to SPICE simulations is made.
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