An overview of the process performance of Stress FreePolishing technology (SFP) [I] for copper removal at sub 90nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed. IntroductionCopper was introduced in the recent past by the IC industry as the material of choice for on-chip metallization. The dual Damascene scheme is used for forming the copper interconnects. Chemical mechanical planarization (CMP) is currently used for removing the copper over the field areas after the trenches and vias are filled. As the technology scales, the need to reduce on-chip capacitance has led to the use of materials with lower dielectric constants. The low mechanical strength of these films can cause delamination with traditional CMP [2]. The delamination issue may become severe with porous ultra low-k films. Removing the copper without exposing the copper-barrier interface andlor barrier-dielectric interface to traditional CMP polishing conditions can reduce the risk of damage to the dielectric film and copper lines. To address this problem, chemical enhanced planarization (CEP) and spin etch planarization (SEP) are proposed alternatives in the ITRS roadmap [3]. This paper reports results from the stress free polishing (SFP) technique, a new technology offered by ACM Research to address Cu removal without delamination when integrated with low-k
Low-K dielectric adhesion problems were observed at M1 and M2 levels during thermal cycling of a flip chip product. Nano-indentation of simple BEOL test structures was used to determine the relative strength of the various interfaces in the BEOL stack. It is observed that the weakest adhesion is associated with the initial stages of the SiCOH low-K dielectric deposition. Adhesion loss related to the SiCN etch stop deposition is not observed.
In the NanoHand project a system consisting of micro/nano based subsystems for automatic handling of nanometer sized objects like carbon nanotubes (CNTs) and nanowires (NWs) will be developed. The goals of the project are driven by the needs of upcoming semiconductor technology. Demonstrators will be built, which have a short term (a) as well as a long term (b) perspective: (a) automated decoration of scanning probe microscope (SPM) probes with (i) CNT-enabled supertips and (ii) supertips grown by focused electron beam induced deposition; (b) handling and assembly of CNTs for the construction of nanoelectronic devices. NanoHand aims to transfer results achieved in laboratories towards industrially applicable, automated handling system for nanoobjects and its applications. This paper reports the technical achievements of the first project year.
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