An overview of stress free polishing of Cu with ultra low-k(k>2.0) films

Abstract

An overview of the process performance of Stress FreePolishing technology (SFP) [I] for copper removal at sub 90nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed. IntroductionCopper was introduced in the recent past by the IC industry as the material of choice for on-chip metallization. The dual Damascene scheme is used for forming the copper interconnects. Chemical mechanical planarization (CMP) is currently used for removing the copper over the field areas after the trenches and vias are filled. As the technology scales, the need to reduce on-chip capacitance has led to the use of materials with lower dielectric constants. The low mechanical strength of these films can cause delamination with traditional CMP [2]. The delamination issue may become severe with porous ultra low-k films. Removing the copper without exposing the copper-barrier interface andlor barrier-dielectric interface to traditional CMP polishing conditions can reduce the risk of damage to the dielectric film and copper lines. To address this problem, chemical enhanced planarization (CEP) and spin etch planarization (SEP) are proposed alternatives in the ITRS roadmap [3]. This paper reports results from the stress free polishing (SFP) technique, a new technology offered by ACM Research to address Cu removal without delamination when integrated with low-k

Planarization Technologies Involving Electrochemical Reactions

“…In the acidic region, just after the Cu surface is first oxidized by chemical oxidizer, the oxidized Cu surface immediately forms a Cu (complex) with the available complex agent. 11.3 are removal rate = 605 nm/min at 3 psi  0.5 m/s = 10.5 kPa m/s [14]. This represents the competing reaction between chemical reactions (1) and (2), and mechanical reaction (3), in accordance with Preston's law.…”

Noncontact Thickness Measurement of Cu Film on Silicon Wafer Using Magnetic Resonance Coupling for Stress Free Polishing Application

“…Under the situation, the strength of material on the silicon wafer decreases and the traditional CMP technique would give rise to damages to the Cu interconnects because of the high downforce from the polishing chuck. To overcome the problem, two-step stress free polishing (SFP) technology has been studied in recent years [4], [5]. For the first step, the traditional CMP process is applied to remove a large portion of the Cu film on the silicon wafer till the thickness of Cu film is reduced to about 200 nm ∼ 300 nm.…”