In the issue of expanding noise levels the world over, road traffic noise is main contributor. The investigation of street traffic noise in urban communities is a significant issue. Ample opportunity has already passed to understand the significance of noise appraisal through prediction models with the goal that assurance against street traffic noise can be actualized. Noise predictions models are utilized in an increasing range of decision-making applications. This study’s main objective is to assess ambient noise levels at major arterial roads of Surat city, compare these with prescribed standards, and develop a noise prediction model for arterial roads using an Artificial Neural Network. The feed-forward back propagation method has been used to train the model. Models have been developed using the data of three roads separately, and one final model has also been developed using the data of all three roads. Among the prediction in three arterial roads, the predicted output result from the model of Adajan-Rander showed a better correlation with a mean squared error (MSE) of 0.789 and R2 value of 0.707. But with the combined model, there is a slight deterioration in mean squared value (MSE) 1.550, with R2 not getting changed much significantly, i.e., 0.755. However, the combined model’s prediction can be adopted due to the variety of data used in its training.
This paper describes the implementation of various line coding schemes using VHDL on Xilinx Spartans-6 XC6SLX45 FPGA platform for the purpose of security, area optimization and can support efficient digital communication in varying channel environment. The choice of line code depends upon presence or absence of DC level, power spectral density, Bandwidth requirement, Bit error rate (BER) performance, ease of clock signal recovery and presence or absence of inherent error detection property. The line encoding schemes used are Unipolar RZ and NRZ, Polar RZ and NRZ, AMI and Manchester coding and Pseudo ternary encoding, Coded Mark Inversion format. Select pin impinged on the chip enables the users to select any one of the line encoding technique according to their requirement. The modeling and simulation of various line codes are implemented on Xilinx design tools and Hardware abstraction completed on Spartan-6 FPGA.
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