Abstract:This paper describes the implementation of various line coding schemes using VHDL on Xilinx Spartans-6 XC6SLX45 FPGA platform for the purpose of security, area optimization and can support efficient digital communication in varying channel environment. The choice of line code depends upon presence or absence of DC level, power spectral density, Bandwidth requirement, Bit error rate (BER) performance, ease of clock signal recovery and presence or absence of inherent error detection property. The line encoding s… Show more
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