As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping processes have been developed to produce the small solder features required for this interconnect technology. These processes differ significantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 lm on 150-lm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.
Detailed observations of the impact of various process parameters on the fracture of brittle structures in low-k dielectric flip chips assembled on organic laminates using lead-free metallurgies are reported. Specifically, a simple model is first presented to evaluate the stresses transmitted to the chip back end of line structures which are susceptible to failure during the reflow at chip joining. These stresses are regulated by creep deformation, so that damage to the chip can be controlled by carefully engineering the creep properties of the solder joints. We introduce new experimental techniques to monitor the creep behaviour of the joints during the reflow. In particular, we describe the use of a laser interferometer technique to monitor the chip curvature with a high sampling rate (few Hz) throughout the reflow. It is shown that these measurements can be used to predict the likelihood of causing brittle fracture in the chip structures. Additionally, we present electron backscatter diffraction (EBSD) data for the microstructure of a large number of solder joints. Using a combination of these theoretical and experimental observations, we derive a complete phenomenology for brittle fractures in the chip during the reflow. The creep-limited stresses are a strong function of solder joint plastic strain rates, which in turn are a strong function of cooling rates during the reflow. Creep properties are also a strong function of the solder metallurgy: reducing the silver content in the SnAgCu alloys results in a higher propensity for creep and correspondingly lower stresses. Thermal treatments at high temperature, such as annealing, can affect the characteristics of the intermetallic compounds, resulting in different creep properties. These trends are observed as the limiting behaviour of the relatively large number of solder joints in typical flip chip packages, but due to the small size of the solder joints (approximately 100 µm in diameter), significant variability is observed from joint to joint in the interconnect array. We link this variability to the joint microstructure by showing that the size and orientation of the few grains generally forming these joints influence the risk to cause damage in the chip.
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