This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a 3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 V and the power consumption is 7.92 W from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 m 256 m in 0.18-m complementary metal-oxide semiconductor technology.Index Terms-Crosstalk, low-noise neural amplifier, noise efficiency factor, nonlinearity, partial OTA sharing technique.

We present a CMOS imager with built-in capability to perform Compressed Sensing coding by Random Convolution. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to complete the acquisition model. The feasibility of the imager and its robustness under noise and non-linearities have been confirmed by computer simulations, as well as the reconstruction tools supporting the Compressed Sensing theory.

A CMOS imager is presented which has the ability to perform localized compressive sensing on-chip. In-pixel convolutions of the sensed image with measurement matrices are computed in real time, and a proposed programmable twodimensional scrambling technique guarantees the randomness of the coefficients used in successive observation. A power and areaefficient implementation architecture is presented making use of a single ADC. A 256×256 imager has been developed as a test vehicle in a 0.18µm CIS technology. Using an 11-bit ADC, a SNR of 18.6dB with a compression factor of 3.3 is achieved after reconstruction. The total power consumption of the imager is simulated at 76.7mW from a 1.8V supply voltage.

No abstract

This article presents a neural recording amplifier suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is the most energy-efficient structure reported to date, which achieves an effective noise efficiency factor (NEF) smaller than the theoretical limit that was claimed in literature for any existing amplifier (NEF=2.02). The proposed technique, which is referred to as partially OTA sharing technique, achieves a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of systematic mismatch on crosstalk between adjacent channels and the trade-off between noise and crosstalk are theoretically analyzed. For an array of four neural amplifiers, simulation results show a midband gain of 39.2 dB and a-3 dB bandwidth from 10 Hz to 10.6 kHz. The input referred noise is simulated to be 2.21 μV rms and the power consumption is 7.92 μW from 1.8 V supply, which refers to NEF=1.8. The worst-case crosstalk within the desired bandwidth is-46.1 dB.