We report the single-electron tunneling behaviour of a silicon nanobridge where the effective island is a single As dopant atom. The device is a gated silicon nanobridge with a thickness and width of ∼20 nm, fabricated from a commercially available silicon-on-insulator wafer, which was first doped with As atoms and then patterned using a unique CMOS-compatible technique. Transport measurements reveal characteristic Coulomb diamonds whose size decreases with gate voltage. Such a dependence indicates that the island of the single-electron transistor created is an individual arsenic dopant atom embedded in the silicon lattice between the source and drain electrodes, and furthermore, can be explained by the increase of the localisation region of the electron wavefunction when the higher energy levels of the dopant As atom become occupied. The charge stability diagram of the device shows features which can be attributed to adjacent dopants, localised in the nanobridge, acting as charge traps. From the measured device transport, we have evaluated the tunnel barrier properties and obtained characteristic device capacitances. The fabrication, control and understanding of such "single-atom" devices marks a further step towards the implementation of single-atom electronics.

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Current–voltage curves of molecular single-electron tunneling transistors are simulated based on a modified theory of single electronics that accounts for the discreteness of the energy spectrum of the molecule. The simulation was performed including effects of energy relaxation of the electrons in the molecule for two limiting cases of fast and slow relaxation, and for both equidistant and randomly spaced energy levels of the molecule. An efficient recursion method allowing a fast calculation of the Gibbs canonical distribution for electrons in the molecule is suggested and realized. A comparison of the simulated I–V curves with the experimental ones shows that the experimental conditions correspond to the slow relaxation case.

Here we present an original CMOS compatible fabrication method of a single-electron transistor structure with extremely small islands, formed by solitary phosphorus dopants in the silicon nanobridge. Its key feature is the controllable size reduction of the nanobridge in sequential cycles of low energy isotropic reactive ion etching that results in a decreased number of active charge centers (dopants) in the nanobridge from hundreds to a single one. Electron transport through the individual phosphorous dopants in the silicon lattice was studied. The final transistor structure demonstrates a Coulomb blockade voltage of ∼30 mV and nanobridge size estimated as [Formula: see text]. Analysis of current stability diagrams shows that electron transport in samples after the final etching stage had a single-electron nature and was carried through three phosphorus atoms. The fabrication method of the demonstrated structure allows it to be modified further by various impurities in additional etching and implantation cycles.

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