Classification is an important task at which both biological and artificial neural networks excel 1,2 . In machine learning, nonlinear projection into a high-dimensional feature space can make data linearly separable 3,4 , simplifying the classification of complex features. Such nonlinear projections are computationally expensive in conventional computers. A promising approach is to exploit physical materials systems that perform this nonlinear projection intrinsically, because of their high computational density 5 , inherent parallelism and energy efficiency 6,7 . However, existing approaches either rely on the systems' time dynamics, which requires sequential data processing and therefore hinders parallel computation 5,6,8 , or employ large materials systems that are difficult to scale up 7 . Here we use a parallel, nanoscale approach inspired by filters in the brain 1 and artificial neural networks 2 to perform nonlinear classification and feature extraction. We exploit the nonlinearity of hopping conduction [9][10][11] through an electrically tunable network of boron dopant atoms in silicon, reconfiguring the network through artificial evolution to realize different computational functions. We first solve the canonical two-input binary classification problem, realizing all Boolean logic gates 12 up to room temperature, demonstrating nonlinear classification with the nanomaterial system. We then evolve our dopant network to realize feature filters 2 that can perform four-input binary classification on the Modified National Institute of Standards and Technology handwritten digit database. Implementation of our material-based filters substantially improves the classification accuracy over that of a linear classifier directly applied to the original data 13 . Our results establish a paradigm of silicon-based electronics for smallfootprint and energy-efficient computation 14 .Doping is a crucial process in semiconductor electronics, where impurity atoms are introduced to modulate the charge carrier concentration. Conventional semiconductor devices operate in the band regime of charge transport, where the delocalization of the charge carriers gives rise to high mobility and a linear response to an applied electric field. At sufficiently low doping concentration and temperature 9,15 , however, delocalization is lost, and carriers move sequentially from dopant atom to dopant atom. This is referred to as the hopping regime 10,11,16 , which exhibits higher resistivity and nonlinearity. Nonlinearity is often undesired, but it is a valuable asset for unconventional computing, that is, for systems that do not follow the Turing model of computation [6][7][8][17][18][19] . Rather than excluding nonlinearity, we can exploit it 12 and manipulate our physical system with artificial evolution to solve computational problems 17 . This evolution in materio has been used, for example, for frequency distinguishing by liquid crystals 18 and robot control with carbon nanotubes 19 . We recently showed that a disordered network of gold...
Electrons and holes confined in quantum dots define an excellent building block for quantum emergence, simulation, and computation. In order for quantum electronics to become practical, large numbers of quantum dots will be required, necessitating the fabrication of scaled structures such as linear and 2D arrays. Group IV semiconductors contain stable isotopes with zero nuclear spin and can thereby serve as excellent host for spins with long quantum coherence. Here we demonstrate group IV quantum dot arrays in silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe) and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N+1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive cross talk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. These results constitute an excellent base for quantum computation with quantum dots and provide opportunities for each platform to be integrated with standard semiconductor manufacturing. * Corresponding Author: m.veldhorst@tudelft.nl arXiv:1909.06575v1 [cond-mat.mes-hall]
Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a 28Si/28SiO2 interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.
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