Novel Vertical and Planar Merged MOS (EUMOS & P M O S ) structures increasing the packaging density for advanced high-speed low-voltage low-power ULSI are examined The W O S and P M O S where electrons and holes move along common channels are simulated using 20-numerical device-circuit simulators (DCS). Various W O S and PMMOS-SOI constructions providing the integration density up to IO9 elements/cm2 (0. I um design rule) at supply voltages 0.2 -0.8 V have been simulated and optimized
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