Novel Vertical and Planar Merged MOS (EUMOS & P M O S ) structures increasing the packaging density for advanced high-speed low-voltage low-power ULSI are examined The W O S and P M O S where electrons and holes move along common channels are simulated using 20-numerical device-circuit simulators (DCS). Various W O S and PMMOS-SOI constructions providing the integration density up to IO9 elements/cm2 (0. I um design rule) at supply voltages 0.2 -0.8 V have been simulated and optimized
Technology and economics trends and concepts of advanced semiconductor manufiacturing are considered. W e DRAM and CMOS technologies are the work horses of modern WI, in many application. the cost of dramatic process changes may not be justified by the benefits. Breakthrough bipolarCMOS technologies, circuits and architectures offer potential advantages over simple sdmg of CMOS. The key to a SUCCeSSfllf stmtegy of competitive deep-submicron ULSIJD-,3D-WSI fabrication as complete systems is flexibility and performauce. Research effort and breakthroughs ace needed to explore more competitive developments for ULSUD,3DWSI manufactunng on Earth and Space. L " g between flexible megafabs, piIot &abs and Spacefabs wll have to be planned for improved performance and reduced cvcle time and cost of competitive advanced prcducts.
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