We demonstrate self-aligned fully-depleted III-V MOSFETs using CMOS-compatible device structures and manufacturable process flows. Processes with good manufacturability and scalability, such as, gate definition and spacer formation using RIE, and formation of self-aligned source/drain extensions (SDE) and self-aligned raised source/drain (RSD), have been established on III-Vs. We demonstrate short-channel devices down to gate length L G = 30 nm. Our best short-channel devices exhibit peak saturation transconductance G MSAT = 1140 μS/μm at L G = 60 nm and supply voltage V DD = 0.5 V.
I. INTRODUCTIONIn the last decade, there has been a renewed interest in III-V materials as a possible replacement of Si as the MOSFET channel because many III-V materials have low electron effective mass m*, high electron mobility μ, and high ballistic velocity v B [1]. Most III-V devices focus on the MOS-HEMT structure [2]-[7], which is a good test vehicle for evaluating the upper limit of III-V FET performance as MOS-HEMT fabrication uses the least-damaging process conditions. MOSHEMTs are, however, not CMOS compatible due to large overlap capacitance induced by thin high-κ dielectric between the gate and RSD, which results in larger circuit delay (Fig. 1). Furthermore, MOS-HEMTs are typically underlapped, which leads to high series resistance R EXT , unless a δ-doping layer is present, which degrades L G scalability [7].In this work, we focus on devices and processes that are CMOS compatible and manufacturable, and include multiple RIE, self-aligned SDEs, and self-aligned RSD. In addition, we use In 0.53 Ga 0.47 As as the channel material instead of In 0.7 Ga 0.3 As or InAs or InSb [2]-[11] because In 0.53 Ga 0.47 As will lead to lower leakage current at L G = 10 nm due to reduced direct source-to-drain tunneling and band-to-band tunneling, even when quantization is taken into account ( Fig. 2(a)). Furthermore, In 0.53 Ga 0.47 As might have electron m* that will provide a better trade-off between density-of-states capacitance C DOS and ballistic velocity v B , thereby optimizing on-current I ON at L G = 10 nm ( Fig. 2(b)) [12].
We demonstrate self-aligned fully-depleted 20-nm-thick In 0.53 Ga 0.47 As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 /sq, respectively. We demonstrate short-channel MOSFETs with gate lengths L G down to 30 nm, low series resistance R EXT = 375 ·μm, and high peak saturation transconductance G MSAT = 1275 μS/μm at L G = 50 nm and drain bias V DS = 0.5 V. We obtain long-channel capacitive inversion thickness T INV = 2.3 nm and effective mobility μ EFF = 650 cm 2 /Vs at sheet carrier density N S = 5 × 10 12 cm −2 . Finally, using a calibrated quasi-ballistic FET model, we argue that for L G ≤ 20 nm, μ EFF ≈ 1000 cm 2 /Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.Index Terms-III-V FETs, MOSFETs.
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