NCFET: Opportunities &amp; challenges for advanced technology nodes

Krivokapić, Zoran; Aziz, Ahmedullah; Song, D.; Rana, Uzma; Galatage, Rohit; Banna, Srinivasa

doi:10.1109/e3s.2017.8246180

Cited by 10 publications

(6 citation statements)

References 2 publications

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“…An important parameter in the design of NCFETs is capacitance matching. The insulating buffer layer thickness is usually designed to optimize capacitance matching 87,88 ; however, the optimization of this para meter is typically based on a model assuming homogen eous polarization, which is not valid for the multidomain case, in which the NC in the ferroelectric is approx imately independent of the dielectric layer thickness above a certain value. Thus, further device modelling that explicitly considers multidomain gates with mobile domain walls is required 89,90 .…”

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

“…Importantly, sub60 mV per decade S is usually observed only over a limited range of gate biases, which has been attributed to difficulties in main taining capacitance matching over the entire subthresh old region as well as in the ON state, owing to the fact that the semiconductor capacitance substantially changes from depletion to inversion. Nevertheless, recent reports of enhanced ONstate currents and transconductance in HfO 2 based FinFETs 87,88,100 , as well as the improvements in short channel effects 100,101 , attributed to NC operation, are very encouraging.…”

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

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Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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, which needs to be positive owing to thermodynamic stability. However, this relation is also true if one of the local effective capacitances, for example, C 1 , is negative, as long as the condition C ≥ 0 is fulfilled. In this scenario, the application of an external voltage V results in V int = V(1 + C 2 /C 1) −1 at the interface between the two dielectrics, such that V int /V > 1 if C 1 < 0. That is, NC of one part of the system enables amplification of the voltage at the interface (fig. 1b). Contrary to the usual decrease in the overall capacitance when a regular (positive) capacitance is added in series, the addition of

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Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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“…∼0 mV/decade at 300 K), improved on-state drive current at a higher temperature [16,17], superior degree of saturation of output current [18], a low leakage current (∼10 12 A µm −1 or below) at a lower threshold voltage (<0.3 V), and reasonable switching speed (not like NEM relay) [19]. On the other hand, circuit-functionality, reliability, cost, or CMOS compatibility of those novel devices are still lacking, to replace conventional MOSFET [3,6,20]. The asymmetric source/drain structure [21] in TFET, IMOS, and FBFET would cause process complexity.…”

Section: Introductionmentioning

confidence: 99%

Understanding of carriers’ kinetic energy in steep-slope P+N+P+N+ feedback field effect transistor

Sung¹,

Shin²

2022

Semicond. Sci. Technol.

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A feedback field-effect transistor (FBFET) takes advantage of the charges accumulated in its potential well and the restriction of carrier flow by its internal potential barrier to achieve superior electrical properties such as a subthreshold swing, threshold voltage, transconductance, and on/off current ratio. However, the device must deal with the modulation of non-uniformity under forward/reverse bias and with completely losing carrier flow control during reverse bias below a certain channel length. In this work, we address these significant issues by focusing on the width of the source/drain and demonstrate the operation of positive feedback in NMOS using only one additional step, resulting in a superior subthreshold swing (~3 mV/decade at 300 K), a low threshold voltage (~ 0.26 V), hysteresis window (0.018 V), and clear saturation region.

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“…One reason for this is that the power consumption of the device is difficult to reduce. In traditional MOSFETs, the sub-threshold swing (SS) of the device is limited by the Boltzmann limit, resulting in the chip power consumption failing to reach the expected target [1][2][3][4][5]. To reduce the device power consumption, several novel device models have been proposed to achieve a sub-threshold swing (SS) lower than 60 mV/dec at room temperature.…”

Section: Introductionmentioning

confidence: 99%

Steep-Slope and Hysteresis-Free MoS2 Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric

Tao

Liu

2022

Nanomaterials

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An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS2 NCFET is fabricated using a single Hf0.5−xZr0.5−xAl2xOy (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the Hf0.5Zr0.5O2 (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 106. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/Al2O3 stack gates.

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NCFET: Opportunities & challenges for advanced technology nodes

Cited by 10 publications

References 2 publications

Ferroelectric negative capacitance

Ferroelectric negative capacitance

Understanding of carriers’ kinetic energy in steep-slope P+N+P+N+ feedback field effect transistor

Steep-Slope and Hysteresis-Free MoS2 Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric

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