14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications

Krivokapić, Zoran; Rana, Uzma; Galatage, Rohit; Razavieh, Ali; Aziz, Ahmedullah; Liu, J.; Shi, Jiajun; Kim, H. J.; Sporer, R.; Serrao, Claudy Rayan; Busquet, A.; Polakowski, P.; Müller, Johannes; Kleemeier, W.; Jacob, Ajey P.; Brown, D.E.; Knorr, A.; Carter, R.; Banna, Srinivasa

doi:10.1109/iedm.2017.8268393

Cited by 154 publications

(91 citation statements)

References 3 publications

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“…An important parameter in the design of NCFETs is capacitance matching. The insulating buffer layer thickness is usually designed to optimize capacitance matching 87,88 ; however, the optimization of this para meter is typically based on a model assuming homogen eous polarization, which is not valid for the multidomain case, in which the NC in the ferroelectric is approx imately independent of the dielectric layer thickness above a certain value. Thus, further device modelling that explicitly considers multidomain gates with mobile domain walls is required 89,90 .…”

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

“…Importantly, sub60 mV per decade S is usually observed only over a limited range of gate biases, which has been attributed to difficulties in main taining capacitance matching over the entire subthresh old region as well as in the ON state, owing to the fact that the semiconductor capacitance substantially changes from depletion to inversion. Nevertheless, recent reports of enhanced ONstate currents and transconductance in HfO 2 based FinFETs 87,88,100 , as well as the improvements in short channel effects 100,101 , attributed to NC operation, are very encouraging.…”

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

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Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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, which needs to be positive owing to thermodynamic stability. However, this relation is also true if one of the local effective capacitances, for example, C 1 , is negative, as long as the condition C ≥ 0 is fulfilled. In this scenario, the application of an external voltage V results in V int = V(1 + C 2 /C 1) −1 at the interface between the two dielectrics, such that V int /V > 1 if C 1 < 0. That is, NC of one part of the system enables amplification of the voltage at the interface (fig. 1b). Contrary to the usual decrease in the overall capacitance when a regular (positive) capacitance is added in series, the addition of

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Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

Section: Device Implementation Work On Ferroelectric Fetsmentioning

confidence: 99%

Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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“…NCFETs are constructed by introducing into the gate stack a layer of a ferroelectric material that acts as a conditionally negative capacitor. Such devices have been demonstrated to achieve a sub-60 mV/dec subthreshold swing [1], [2] and consequently they are being pursued as a means to scale down supply voltage without loss of performance [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Random discrete dopant induced variability in negative capacitance transistors

Dutta

Georgiev

Asenov

2018

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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In this work we investigate the impact of random discrete dopants (RDD) induced statistical variability in ferroelectric negative capacitance field effect transistors (NCFETs). We couple the 3D 'atomistic' statistical device simulator GARAND with the Landau -Khalatnikov equation of the ferroelectric for this study. We find that the negative capacitance effect provided by the ferroelectric layer can lead to suppression of the RDD induced variability in the threshold voltage (Vt), OFF-current (IOFF), and ON-current (ION). This immunity to RDD induced variability is found to increase with increase in the ferroelectric thickness.

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“…Several models of quasi-static NC associated with domain wall motion in a multiple-domain system have been also proposed [9][10][11][12][13] . Meanwhile, steep SS values have been demonstrated by incorporating FE/PE gate stacks into FETs with various FE materials [14][15][16] , various channel materials 15,[17][18][19] and various FET structures 14,[20][21][22][23][24] .…”

mentioning

confidence: 99%

Stepwise internal potential jumps caused by multiple-domain polarization flips in metal/ferroelectric/metal/paraelectric/metal stack

Toriumi

2020

Nat Commun

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Negative capacitance (NC) effects in ferroelectric/paraelectric (FE/PE) stacks have been recently discussed intensively in terms of the steep subthreshold swing (SS) in field-effect transistors (FETs). It is, however, still disputable to stabilize quasi-static-NC effects. In this work, stepwise internal potential jumps in a metal/FE/metal/PE/metal system observed near the coercive voltage of the FE layer are reported through carefully designed DC measurements. The relationship of the internal potential jumps with the steep SS in FETs is also experimentally confirmed by connecting a FE capacitor to a simple metal-oxidesemiconductor FET. On the basis of the experimental results, the observed internal potential jumps are analytically modelled from the viewpoint of bound charge emission associated with each domain flip in a multiple-domain FE layer in a FE/PE stack. This view is different from the original NC concept and should be employed for characterizing FE/PE gate stack FETs.

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14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications

Cited by 154 publications

References 3 publications

Ferroelectric negative capacitance

Ferroelectric negative capacitance

Random discrete dopant induced variability in negative capacitance transistors

Stepwise internal potential jumps caused by multiple-domain polarization flips in metal/ferroelectric/metal/paraelectric/metal stack

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