Random discrete dopant induced variability in negative capacitance transistors

Abstract

In this work we investigate the impact of random discrete dopants (RDD) induced statistical variability in ferroelectric negative capacitance field effect transistors (NCFETs). We couple the 3D 'atomistic' statistical device simulator GARAND with the Landau -Khalatnikov equation of the ferroelectric for this study. We find that the negative capacitance effect provided by the ferroelectric layer can lead to suppression of the RDD induced variability in the threshold voltage (Vt), OFF-current (IOFF), and ON-current (ION). This immunity to RDD induced variability is found to increase with increase in the ferroelectric thickness.

Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters

“…Furthermore, RDF‐induced fluctuation of these parameters can also be successfully suppressed, i.e., σV th , σ SS, and σI OFF of n‐NCFET and p‐NCFET are reduced as compared to the baseline transistors in both the linear and saturated regions. Note that the σI ON of the NCFETs increases with the FE capacitor applied, but the relative standard deviations are smaller (as also demonstrated in [16]). Because I ON in NCFETs is obviously higher than in the baseline MOSFETs, it is more significant to compare the relative standard deviation than the standard deviation.…”

“…Li et al [15] demonstrated that propagation delay is strongly dependent on FE damping constant, which is closely related to the FE response time. Furthermore, there also have been only a few reports concerning variability in NCFETs [16, 17] and NC‐FinFETs [18–21]. The research in [16] focused only on V th , I ON , and I OFF variations due to typical current–voltage characteristics in NCFETs with the possibility of negative differential resistance [22, 23] and negative drain induced barrier lowering (DIBL) phenomena [23].…”

“…Furthermore, there also have been only a few reports concerning variability in NCFETs [16, 17] and NC‐FinFETs [18–21]. The research in [16] focused only on V th , I ON , and I OFF variations due to typical current–voltage characteristics in NCFETs with the possibility of negative differential resistance [22, 23] and negative drain induced barrier lowering (DIBL) phenomena [23]. In addition to investigating work function variation (WFV)‐ and line‐edge roughness (LER)‐induced variability [18–20], Dutta et al [21] investigated the sensitivity to process variation in critical device dimensions and FE parameters, and found that NC‐CMOS ring oscillators can effectively reduce delay variability.…”

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework

“…NCFETs have been realized in various architectures, including FinFET [73] and nanowire FET [74]. In addition to the prospects of improved nominal device performance [75], NCFETs have been shown to be more immune to statistical variability compared to their conventional counterparts [76][77][78][79]. NCFETs also have shown promising circuit applications [80,81].…”

Interplay of RDF and Gate LER Induced Statistical Variability in Negative Capacitance FETs

“…Variability induced by the statistical nature of RDF and gate LER play critical role in MOSFETs, and their impact in limiting the performance of existing CMOS technologies has been investigated comprehensively using 3D simulations in the past [6], [7]. Analysis of process induced variability in the critical dimensions of NC-FinFETs was reported earlier in [8], while the suppression of RDF induced variability in bulk NCFETs was recently analyzed [9]. In this paper we extend the work to include gate LER and its interplay with RDF.…”