Abstract-Contemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts. In this letter, we present a new device structure where the carrier injection takes place through silicon slabs of only a few nanometer thick. Its external quantum efficiency of 1.4 · 10 −4 at room temperature, with a spectrum peaking at 1130 nm, is almost two orders higher than reported thus far on SOI. The structure diminishes the dominant role of nonradiative recombination at the n + and p + contacts, by confining the injected carriers in an SOI peninsula. With this approach, a compact infrared light source can be fabricated using standard semiconductor processing steps.
In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ⩽20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.
Abstract-The infrared light emission of forward-biased silicon diodes is studied. Through ion implantation and anneal, dislocation loops were created near the diode junction. These loops suppress the light emission at the band-to-band peak around 1.1 µm. The so-called D1 line at 1.5 µm is strongly enhanced by these dislocation loops. We report a full study of photoluminescence and electroluminescence of these diodes. The results lead to new insights for the manufacturing approach of practical infrared light sources in integrated circuits.
Device scaling has been a subject of research for both optoelectronics and electronics. In order to investigate the electronic properties of scaled devices we studied lateral p-in structures using thin silicon on insulator (SOI) or poly-Si layers of varying dimension. With the help of these structures we try to explain the size dependencies on electronic transport properties. Further, we also propose a new device concept called charge plasma diode. Index Terms-diode, p-in diode, charge plasma (CP) diode, silicon-on-insulator (SOI), buried oxide (BOX), quantum confinement, band gap widening.
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