Embedded processors are increasingly being used in digital consumer appliances such as cellular phones, digital still/video cameras, and car navigation systems. They must deliver high performance with reasonable area and power consumption and be flexible enough to meet a wide range of requirements for various applications. However, only a few devices targeting large markets, such as cellular phones, can bear the cost of a special-purpose processor design. An alternative is to use optional modules, such as DSPs and floating-point units (FPUs), to augment the capabilities of the basic processing core. An optional DSP can be added as an execution unit, which is much smaller than a full DSP core, to effectively accelerate standardized applications such as multimedia [1]. While PCs and game consoles can bear the high cost of special graphics hardware much larger than a processor core [2][3], other digital consumer appliances cannot. An optional FPU handles a wide dynamic range of data thus simplifying programming, especially for graphics acceleration. Therefore, an optional FPU is a good approach to achieve high graphics performance with an embedded processor [4]. A flexible SuperH TM (SH) processor core is developed to meet these requirements.The specifications of the SH processor core are shown in Fig. 18.5.1. The use of an on-chip RAM ensures real-time response, a key feature of embedded processors. Micrographs of the standard-version processor core and the first product chip for car navigation systems are shown in Fig. 18.5.2. A low power version is integrated in an application processor for cellular phones [5].
This paper is a study of four-dimensional automata. Recently, due to the advances in many application areas such as dynamic image processing, computer animation, augmented reality(AR), and so on, it is useful for analyzing computation of four-dimensional information processing (three-dimensional pattern processing with time axis) to explicate the properties of four-dimensional automata. From this point of view, we have investigated many properties of four-dimensional automata and computational complexity. On the other hand, the class of sets accepted by probabilistic machines have been studied extensively. As far as we know, however, there is no results concerned with four-dimensional probabilistic machines. In this paper, we introduce four-dimensional probabilistic finite automata, and investigate some accepting powers of them.
Concentration index filter is a kind of spatial filters of images, and its typical application is diagnosis from medical images. This paper presents a dedicated computing engine for concentration index filtering. Original algorithm is modified to extract full parallelism and data width is optimized for maximizing clock speed and minimizing hardware scale. Evaluation results reveal that the system runs 100 times faster than current workstation and enables real-time diagnosis. ConcentrationIndex Filter Not small number of image processing applications suit FPGA-based hardware, as reported in many papers ([1] for example). In this paper, we focus our mind on the concentration index and present an efficient architecture of an FPGA-based system.Concentration index[2] is a characteristicmeasurement which indicates the degree of concentration of lines to a certain point in an image. For each pixel in the image, all the neighboring lines are evaluated whether they direct to the point. When the resulting concentration index scores high, it means that neighboring lines concentrate to the point. Figure 1 illustrates the calculation of concentration index at a point P. Any point Q in the neighboring area (R) of p has a line element whose length is dx and angle a. r is the length of PQ. The concentration index at the point p (we denote C(P)) is defined as follows:tational structure is rather simple. So the operation is suitable for FPGA-based systems. Thus we propose an FPGA-based concentration index operation engine with the following two features: (a) it offers sufficiently high performance and flexibility by introducing FPGA, and (b) it should be a scalable system by employing multiple FPGAs. ComplexityReduction As the number of possible patterns of line elements are eight, combinations of dx and 0. in Equation (1) are limited, and thus we can use pre-computed values of (dxlcoso.l/r) and dx/r in the equation. This reduces computational complexity considerably. ParallelismExtraction A naive algorithm derived from Equation (1) is changed to fit for hardware execution. Figure 2 shows the resulting algorithm. We can find rich parallelism in the kernel loop.
Blum and Hewitt first proposed two-dimensional automata as computational models of two-dimensional pattern processing-two-dimensional finite automata and marker automata, and investigated their pattern recognition abilities in 1967. Since then, many researchers in this field have investigated the properties of automata on two-or three-dimensional tapes. On the other hand, the question of whether or not processing four-dimensional digital patterns is more difficult than processing two-or three-dimensional ones is of great interest from both theoretical and practical standpoints. Thus, the study of four-dimensional automata as the computational models of four-dimensional pattern processing has been meaningful. From this point of view, we are interested in four-dimensional computational models, In this paper, we introduce a new four-dimensional computational model, k-neighborhood template A-type three-dimensional bounded cellular acceptor on four-dimensional input tapes, and investigate about hierarchy based on configuration-reader about this model.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.