Concentration index filter is a kind of spatial filters of images, and its typical application is diagnosis from medical images. This paper presents a dedicated computing engine for concentration index filtering. Original algorithm is modified to extract full parallelism and data width is optimized for maximizing clock speed and minimizing hardware scale. Evaluation results reveal that the system runs 100 times faster than current workstation and enables real-time diagnosis. ConcentrationIndex Filter Not small number of image processing applications suit FPGA-based hardware, as reported in many papers ([1] for example). In this paper, we focus our mind on the concentration index and present an efficient architecture of an FPGA-based system.Concentration index[2] is a characteristicmeasurement which indicates the degree of concentration of lines to a certain point in an image. For each pixel in the image, all the neighboring lines are evaluated whether they direct to the point. When the resulting concentration index scores high, it means that neighboring lines concentrate to the point. Figure 1 illustrates the calculation of concentration index at a point P. Any point Q in the neighboring area (R) of p has a line element whose length is dx and angle a. r is the length of PQ. The concentration index at the point p (we denote C(P)) is defined as follows:tational structure is rather simple. So the operation is suitable for FPGA-based systems. Thus we propose an FPGA-based concentration index operation engine with the following two features: (a) it offers sufficiently high performance and flexibility by introducing FPGA, and (b) it should be a scalable system by employing multiple FPGAs. ComplexityReduction As the number of possible patterns of line elements are eight, combinations of dx and 0. in Equation (1) are limited, and thus we can use pre-computed values of (dxlcoso.l/r) and dx/r in the equation. This reduces computational complexity considerably. ParallelismExtraction A naive algorithm derived from Equation (1) is changed to fit for hardware execution. Figure 2 shows the resulting algorithm. We can find rich parallelism in the kernel loop.
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