An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

Arakawa, Fumio; Yoshinaga, Tsunehiro; Hayashi, Tomoichi; Kiyoshige, Yoshikazu; Okada, Takashi; Nishibori, Masakazu; Hiraoka, Toshiro; Ozawa, M.; Kodama, Tetsuya; Irita, Takahiro; Kamei, Takeshi; Itō, Makoto; Nitta, Yusuke; Nishii, O.; Hattori, Toshihiro

doi:10.1109/isscc.2004.1332730

Cited by 33 publications

(9 citation statements)

References 2 publications

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“…5. The energy-and areaefficiency of the ASIC built using our methodology compares favorably to recently published baseband communications and media processors with high energy-efficiencies [11] and the high area-efficiencies [12]. Subsequently, few other ASICs, including multi-standard FIR and UWB processor were recently designed.…”

Section: Architecture Exploration In Simulinkmentioning

confidence: 70%

ASIC Design and Verification in an FPGA Environment

Marković

Chang

Richards

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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--A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4×4 MIMO signal processing.

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Section: Architecture Exploration In Simulinkmentioning

confidence: 70%

ASIC Design and Verification in an FPGA Environment

Marković

Chang

Richards

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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“…We considered the SH-4A processor [8] as a scalar core to which the arithmetic accelerator and the onchip memory were added. We developed a clock-level simulator that executes the SH-4A, SIMD, and vector instruction sets.…”

Section: A Evaluation Environmentmentioning

confidence: 99%

Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators

Takahashi

Sato

Takahashi

et al. 2008

2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems

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In this paper, we design an on-chip memory processor with arithmetic accelerators, which are expected to improve power consumption. In addition, we evaluate the power performance of the processor. We propose implementing vector-type arithmetic accelerators and SIMD-type arithmetic accelerators in the on-chip memory processor. The evaluation results obtained using our simulator indicate that the performance of the 4 FMAs SIMD-type accelerators is similar to that of the 4 FMAs vector-type accelerators on DAXPY, Livermore kernel 1 and 3. However, the performance of the 4 FMAs vector-type accelerator exceeds that of the 4 FMAs SIMD-type accelerator with respect to matrix multiplication and QCD because of difference in element size of the registers. On Livermore kernel 7, the power performance of the 4 FMAs SIMD-type accelerators exceeds that of the 4 FMAs vectortype because of register reuse. However, the 16 FMAs vectortype accelerators have an advantage in almost all simulations, excluding main memory bandwidth intensive benchmarks.

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“…It integrates the FPU, whose peak performance is 2.8 GFLOPS, as a coprocessor, and maintains code compatibility with the SH-4. It achieves 36M polygons/s with its FPU measured using a simple geometry benchmark program [8].…”

Section: Sh-x Core Specificationsmentioning

confidence: 99%

Development of processor cores for digital consumer appliances

Arakawa

Yamada

Okada

et al. 2006

Systems & Computers in Japan

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SUMMARYEmbedded processors are increasingly being used in digital consumer appliances such as cellular phones, digital still/video cameras, and car navigation systems. They must therefore deliver high performance within a reasonable area and power consumption level, and be flexible to meet a wide range of requirements for various applications. In this paper, we introduce our latest processor core SH-X developed under the above background. The low-power version of the SH-X core achieves 360 MIPS with a power of 80 mW resulting in the high power-performance ratio of 4500 MIPS/W. The standard version achieves 720 MIPS with a power of 250 mW, 2.8 GFLOPS, and 36M polygons/s graphics performance. The leak currents in the resume standby and U-standby modes are 100 and 10 µA, respectively. The resume standby mode can return the status before the standby in only 3 ms, while the U-standby mode requires reset sequence to restart.

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An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

Cited by 33 publications

References 2 publications

ASIC Design and Verification in an FPGA Environment

ASIC Design and Verification in an FPGA Environment

Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators

Development of processor cores for digital consumer appliances

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