ASIC Design and Verification in an FPGA Environment

Abstract

--A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4×4 MIMO signal processing.

Design and rapid prototyping of SCA-compliant public safety P25 waveform and P25–FM3TR–VoIP bridge

“…Simulink is intuitive for both algorithm development and hardware design, as it provides a layered view of the system from an abstract system block diagram to a detailed circuit implementation. Advocates from industry and academia have proposed using Simulink as the design entry for ASIC or FPGA development [9][10][11]. There are both commercial and public domain tools available that directly translate a bit-true and cycle-true Simulink model built with hardware equivalent blocks into hardware designs.…”

“…Therefore, the FPGA design entry barrier is lowered for many system and algorithm designers. Furthermore, joint algorithm, architecture and circuit optimization can be performed in the Simulink environment [9,10]. Hence, Simulink-based hardware design is ideal for fast prototyping of signal processing systems.…”

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

“…The chip was synthesized using a customized design flow [28] and fabricated by TSMC in 65 nm CMOS. Although the core size of the chip is 1.53 mm by 1.53 mm, the design is pad-limited with a utilization factor of 15.1%.…”

A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS

“…The outputs of the ASIC are captured and fed into block RAMs for analysis . The I/O interface between the client PC and the IBOB board is built on the BPS environment [8]. The real-time operation and easy programmability ease the testing and data analysis .…”