A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

Abstract

Abstract-The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Power consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error.

Digital synchronization for symbol-spaced IEEE802.11ad Gigabit mmWave systems

“…5. For this type of equalizer it is irrelevant whether interference appears before or after the equalization window, for a linear time-domain receiver which relies heavily on decision feedback as in [14] precursor interference is way more problematic. After determining the best synchronization point, the aligned CIRh and the data streamr are forwarded to the equalizer.…”

A decision feedback equalizer with channel-dependent power consumption for 60-GHz receivers

“…Such a specification could be supported by a scheme such as the one in [4]: Assuming a targeted rate of 2GS/s, a fixed-length clocked delay line of 40 delay elements would drive five 40:1 multiplexers. Introducing redundant delay elements could lead to simpler overhead routing, as in [3]. Nonetheless, all possible tap delay arrangements should be able to be addressed.…”

“…This has resulted in demonstrating designs with substantially lower power requirements. For example, 5.6mW of power are required for 2 Gbps of operation in the purely digital approach of [3]. From a system architecture standpoint however, digital DFE implementations imply the use of a high-speed and potentially high-resolution analog-to-digital converter (ADC), in order to sample the RF baseband.…”

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

“…Many different architectures have been proposed for SC mmWave systems [1]- [4], but to the best of our knowledge, the feasibility of sequence estimation has not been explored for such an application. A full sequence-estimation (SE) results in maximum likelihood (ML) performance and hence exhibits an inherent performance advantage over any linear equalizer in the presence of inter-symbol-interference.…”