Biologically-inspired packet switched network on chip (NoC) based hardware spiking neural network (SNN) architectures have been proposed as an embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in SNNs require large distributed on-chip memory, which poses serious challenges for compact hardware implementation of such architectures. Based on the structured neural organisation observed in human brain, a modular neural networks (MNN) design strategy partitions complex application tasks into smaller subtasks executing on distinct neural network modules, and integrates intermediate outputs in higher level functions. This paper proposes a hardware modular neural tile (MNT) architecture that reduces the SNN topology memory requirement of NoC-based hardware SNNs by using a combination of fixed and configurable synaptic connections. The proposed MNT contains a 16:16 fully-connected feed-forward SNN structure and integrates in a mesh topology NoC communication infrastructure. The SNN topology memory requirement is 50 % of the monolithic NoC-based hardware SNN implementation. The paper also presents a lookup table based SNN topology memory allocation technique, which further increases the memory utilisation efficiency. Overall the area requirement of the architecture is reduced by an average of 66 % for practical SNN application topologies. The paper presents micro-architecture details of the proposed MNT and digital neuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65 nm low-power CMOS technology. The evolvable capability of the proposed MNT and its suitability for executing subtasks within a MNN execution architecture is demonstrated by successfully evolving benchmark SNN application tasks representing classification and non-linear control functions. The paper

This communication presents a new direction-of-arrival based tracking method, using shaped beam patterns. The advantage of this method is that the direction of a signal can be estimated based on a single output (analog) beamformer, without having to scan over multiple angles. Simulations indicate that, although arrays consisting of 8 to 16 antennas are preferable, the minimum array size is 4. A single array can cover a scan angle of roughly 120 and the direction of arrival can be estimated with an RMS error of 2 .Index Terms-Analog systems, direction of arrival estimation, shaped beam antennas, tracking.

Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructure offers scalable connectivity for spike communication in hardware SNN architectures. However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency. This packet latency jitter alters spike timings and distorts the information conveyed on the synaptic connections in the SNN, resulting in unreliable application behaviour. This paper presents a simulation-based analysis of this synaptic information distortion in NoC based hardware SNNs.The paper proposes a ring topology interconnect for spike communication between neural tiles, and a timestamped spike broadcast flow control scheme that offers fixed spike transfer latency. The proposed architectural technique is evaluated using spike rates employed in previously reported hardware SNN applications. Results indicate that the proposed interconnect offers fixed spike transfer latency and eliminates the associated information distortion.The paper presents the micro-architecture of the proposed ring router. The ring interconnect architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. Silicon area comparisons for various ring sizes are presented. Limitations on the scalability of the proposed ring architecture and selection of the optimal ring size based on spike rate resolution and hardware resources are discussed. A hierarchical, mesh topology NoC architecture with a 4 × 8 modular neural elements supporting 896 neurons and 72K synapses on a Xilinx Virtex-6 XC6VLX240T FPGA device is presented.

A procedure to synthesize asymmetrically shaped beam patterns is developed for planar antenna arrays. As it is based on the quasi-analytical method of collapsed distributions, the main advantage of this procedure is the ability to realize a shaped (null-free) region with very low ripple. Smooth and asymmetrically shaped regions can be used for Direction-of-Arrival estimation and subsequently for efficient tracking with a single output (fully analog) beamformer.

Millimeter wave (mmWave) communication is being seen as a disruptive technology for 5G era. In particular, 60 GHz frequency band has emerged as a promising candidate for multi-Gbps connectivity in indoor and hotspot areas. In terms of network architecture, cloud radio access network (CRAN) has emerged as the most promising architectural alternative to enable efficient baseband processing and dynamic resource allocation in 5G communications. In this article, we propose micro-CRAN (mCRAN) -a multi-gigabit indoor network architecture which leverages availability of high bandwidth in 60 GHz frequency band. We have discussed in detail about the requirements and research challenges for various system modules for mCRAN based network architecture. We have also investigated the feasibility of IEEE 802.11ad MAC protocol for the proposed mCRAN architecture. We discuss the challenges related to 60 GHz beamforming, medium access mechanisms and network architecture, and propose solutions to address them.