Fixed latency on-chip interconnect for hardware spiking neural network architectures

Pande, Sandeep; Morgan, Frank; Smit, Gerardus Johannes Maria; Bruintjes, Tom; Rutgers, B; McGinley, Brian; Cawley, Seamus; Harkin, Jim; McDaid, LJ

doi:10.1016/j.parco.2013.04.010

Cited by 29 publications

(13 citation statements)

References 36 publications

(50 reference statements)

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“…Although the NoC paradigm offers a scalable communication infrastructure for SNN's hardware architectures, it can result in undesired jitter in spike transfer timing. To solve the timing constraint of spike delivery in the NoC-based SNNs' hardware, Pande et al [17] has proposed a ring topology with fixed spike communication latency. This work suggests a novel broadcast dataflow control based on the timestamping technique.…”

Section: Non-mesh-based Interconnectsmentioning

confidence: 99%

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Nabavinejad

Baharloo

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Deep Neural Networks (DNNs) have shown significant advantages in many domains, such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations. However, due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the huge communication overheads and storage requirements. As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study. Currently, a large body of research aims to find an efficient on-chip interconnection to achieve low-power and high-bandwidth DNN computing. This paper provides a comprehensive investigation of the recent advances in efficient on-chip interconnection and design methodology of the DNN accelerator design. First, we provide an overview of the different interconnection methods on the DNN accelerator. Then, the interconnection methods on the non-ASIC DNN accelerator will be discussed. On the other hand, with the flexible interconnection, the DNN accelerator can support different computing flow, which increases the computing flexibility. With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper. Finally, we investigate the emerging interconnection technologies (e.g., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs. With this article, the readers are able to: 1) understand

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Section: Non-mesh-based Interconnectsmentioning

confidence: 99%

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Nabavinejad

Baharloo

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…The architecture suffers from wire/router physical limitations. On the other hand, a ring topology interconnect architecture was proposed in [37] to achieve fixed latency.…”

Section: B Spike Routing 2d Network-on-chipmentioning

confidence: 99%

Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems

Ikechukwu

Abdallah

2019

IEEE Access

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Neuromorphic computing systems are an emerging field that takes its inspiration from the biological neural architectures and computations inside the mammalian nervous system. The spiking neural networks (SNNs) mimic real biological neural networks by conveying information through the communication of short pulses between neurons. Since each neuron in these networks is connected to thousands of others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, very low communication latency is also necessary. On the other hand, the combination of Two-dimensional Networks-on-Chip (2D-NoC) and Three-dimensional Integrated Circuits (3D-ICs) can provide a scalable interconnection fabric in large-scale parallel SNN systems. Although the SNNs have some intrinsic fault-tolerance properties, they are still susceptible to a significant amount of faults; especially, when we talk about integrating the large-scale SNN models in hardware. Consequently, the need for efficient solutions capable of avoiding any malfunctions or inaccuracies, as well as early fault-tolerance assessment, is becoming increasingly necessary for the design of future large-scale reliable neuromorphic systems. This paper first presents an analytical model to assess the effect of faulty connections on the performance of a 3D-NoC-based spiking neural network under different neural network topologies. Second, we present a fault-tolerant shortest-path k-means-based multicast routing algorithm (FTSP-KMCR) and architecture for spike routing in 3D-NoC of spiking neurons (3DFT-SNN). Evaluation results show that the proposed SP-KMCR algorithm reduces the average latency by 12.2% when compared to the previously proposed algorithm. In addition, the proposed fault-tolerant methodology enables the system to sustain correct traffic communication with a fault rate up to 20%, while only suffering 16.23% longer latency and 5.49% extra area cost when compared to the baseline architecture.INDEX TERMS Spiking neural networks, performance assessment, fault-tolerant, k-means based multicast routing, scalable architecture.

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“…Though NoC has many important advantages, it has a serious performance limitation such as high power consumption and latency. The traditional NoC with wired communication has a large number of functional nodes reduces its performance [8].…”

Section: B Nano Machine Based Hybrid Nocmentioning

confidence: 99%

Nano Machine-based Hybrid 3D Network-on-Chip (NoC) using 18nm tsmc Technology

Balamurugan*,

Shijukumar

2019

IJEAT

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Network-on-Chip paradigm is an emerging technology that provides communication between the Intellectual Property cores in System-on-Chip (SoC). The drastic development of nanotechnology supports the making of Intellectual property cores with small area, less power dissipation, improvement in latency and achieves high speed. The neural systems that emulate biological sensory capability on reconfigurable hardware are the key requirement in the field of Neuro-Engineering. Nano-neural connectivity technique is highly needed in order to implement reconfigurable Neural Networks (NNs) on-chip. This paper proposes a novel Nano Machine based Hybrid 3D Network-on-Chip for the emulation of a third-generation (3G) Neural Network model called Spiking Neural Network (SNN). This Hybrid Network-on-Chip uses a Nanomachine Transceiver with Carbon nanotube antenna which uses the novel pulse-based technique to transfer the packets between the subnet of NoC to reduce the latency. The experimental result of this work shows the improvement in latency of Nano machine-based NoC compared to the previously reported work for 18 nm TSMC technology.

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Fixed latency on-chip interconnect for hardware spiking neural network architectures

Cited by 29 publications

References 36 publications

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems

Nano Machine-based Hybrid 3D Network-on-Chip (NoC) using 18nm tsmc Technology

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