Determining the time separation of events is a fundamental problem in the analysis, synthesis, and optimization of concurrent systems. Applications range from logic optimization of asynchronous digital circuits to evaluation of execution times of programs for real-time systems. We present an e cient algorithm to nd exact (tight) bounds on the separation time of events in an arbitrary process graph without conditional behavior. The algorithm is based on a functional decomposition technique that permits the implicit evaluation of an in nitely unfolded process graph.

We present a novel set of tools for performing symbolic timing verification of timing diagrams. The tools are multi-purpose with uses in verification, derivation of synthesis constraints, and design evaluation. Our methodology is based on using techniques for manipulating Presburger formulas. We demonstrate using several interesting examples that the method is efficient in practice and should be considered for inclusion in commercial tools. 0 This work was supported by an NSF RIA Award (MIP-9410279). 1 Sometimes the term "symbolic verification" is used to describe a verification methodology (e.g., using BDDs to symbolically explore a state space) but, in our case, the actual input and output make use of symbolic variables. Design Automation Conference R

Symbolic timing verification is a powerfur extension to traditional constraint checking that allows delays and constraints to be expressed as symbolic variables. In this paper, we present an approach to symbolic timing verification using constraint logic programming techniques. The techniques are quire powerful in that they yield not only simple bounds on delays but also relate the delays in linear inequalities so that tradeoffs are apparent. We model circuits as communicating processes and our current implementation can verifr a large class of h d synchronous and asynchronous specifications. The utility of the approach is illustrated with some examples.

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