Symbolic timing verification of timing diagrams using Presburger formulas

Abstract

We present a novel set of tools for performing symbolic timing verification of timing diagrams. The tools are multi-purpose with uses in verification, derivation of synthesis constraints, and design evaluation. Our methodology is based on using techniques for manipulating Presburger formulas. We demonstrate using several interesting examples that the method is efficient in practice and should be considered for inclusion in commercial tools. 0 This work was supported by an NSF RIA Award (MIP-9410279). 1 Sometimes the term "symbolic verification" is used to describe a verification methodology (e.g., using BDDs to symbolically explore a state space) but, in our case, the actual input and output make use of symbolic variables. Design Automation Conference R

Reasoning about synchronization in GALS systems

“…This contrasts with the work of [3,6,17,21,30], where the goal is to compute performance metrics and bounds on time separation of events. The work that comes closest to our are those of Amon et al [1] and Clariso et al [9]. A detailed comparison of our approach with these two earlier work is provided in Section 4.…”

“…ATDs are syntactically similar to commonly used waveform diagrams, timing diagrams [1,12], event-rule systems [3,21], event graphs [30], action diagrams [17], timing constraint graphs [6] and message sequence charts [15]. However, the analysis of interface timing constraints using ATDs differs from earlier approaches, as will be elaborated in Section 3.…”

“…Note that the ability to represent symbolic timing constraints between events is a powerful feature, and distinguishes ATDs as also the work of Amon et al [1], Fisler [12] and Clariso et al [9] from several earlier work [3,6,17,21,30]. The ability to represent assume and guarantee constraints of min, max and linear types in the same diagram makes it possible to perform more detailed analysis using ATDs than is possible with the representations used in [3,6,15,21].…”

“…While representations similar to ATDs have been used earlier [1,3,6,12,17,21,30], applying these earlier approaches to our problem would require the designer to manually (or otherwise) identify all possible scenarios of interaction between sequencing and synchronization constraints, and then represent them explicitly in a combined diagram. This poses practical difficulties in a design-analyze-redesign setting, where a designer may wish to go through several iterations of modifying sequencing and synchronization constraints.…”

Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach

“…Moreover, the computational times for deciding the satisfiability for RPS is less than that of Presburger Sentences. RPS and original Presburger Sentences have been successfully applied to the verification of logical designs and network design protocols [10,14,3,25,4]. Tools [23,24] are available for the verification of RPS and Presburger sentences.…”