An approach to symbolic timing verification

Amon, Tod Tracy; Boriello, G.

doi:10.1109/dac.1992.227769

Cited by 17 publications

(10 citation statements)

References 6 publications

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“…An application of constraint logic programming over rational numbers, CLP( ), has been studied in Amon and Boriello [1992]. The authors use the constraint programming approach for symbolic timing verification.…”

Section: Related Workmentioning

confidence: 99%

Constraints-driven scheduling and resource assignment

Kuchcinski

2003

ACM Trans. Des. Autom. Electron. Syst.

118

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This paper describes a new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system-level synthesis. It addresses assignment of resources for operations and tasks as well as their static, off-line scheduling. Different heterogeneous constraints are considered for these problems. These constraints can be grouped into two classes: problem-specific constraints and design-oriented constraints. They are uniformly modeled, in our approach, by finite domain (FD) constraints and solved using related constrained programming (CP) techniques. This provides a way to improve quality of final solutions. We have developed in Java a constraint solver engine, JaCoP (Java Constraint Programming), to evaluate this approach. This solver and a related framework make it possible to model different resource assignment and scheduling problems, and handle them uniformly. The JaCoP prototype system has been extensively evaluated on a number of HLS and system-level synthesis benchmarks. We have been able to obtain optimal results together with related proofs of optimality for all HLS scheduling benchmarks and for all explored design styles (except one functional pipeline design). Many system-level benchmarks can also be solved optimally. For large randomly generated task graphs, we have used heuristic search methods and obtained results that are 1-3% worse than lower bounds or optimal results. These experiments have proved the feasibility of the presented approach.

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Section: Related Workmentioning

confidence: 99%

Constraints-driven scheduling and resource assignment

Kuchcinski

2003

ACM Trans. Des. Autom. Electron. Syst.

118

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“…Path tracing has been combined with state transition graph (STG) analysis [12] for a specific class of designs -CPUs partitioned 1 In contrast, STGs of gate or register transfer level circuits are too large to be represented explicitly and/or take too much time to be built.…”

Section: A Classificationmentioning

confidence: 99%

“…Transformation on OEgraphs [1] which model behavior and timing together is applicable to a general class of designs. However, the transformation rules are adhoc and do not adequately handle the large degree of concurrency encountered for a large number of components.…”

Section: No Inputmentioning

confidence: 99%

“…Symbolic delays enables the modeling of blocks that are not yet designed; the generated symbolic constraints would provide design constraints for the block. Only one of the existing timing verifiers [1] generates symbolic constraints. mtv uses min-max delays, but can be extended to other delay models.…”

Section: Symbolic Vs Numeric Delay Attributesmentioning

confidence: 99%

“…[3] STG analysis [12] true sens. [6,7] on OEgraphs [1] vectors Causality graph [13] Sequential path tracing [mtv] into datapath and controller. This approach is limited to fully synchronous designs where clock gating (and hence multi-cycle paths) is allowed only in the datapath using signals generated by the controller that takes the op-code bits as input.…”

Section: No Inputmentioning

confidence: 99%

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Automated multi-cycle symbolic timing verification of microprocessor-based designs

Gupta

Siewiorek

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Timing verification ascertains whether timing checks on components in a circuit are satisfied given component delay models. This paper addresses timing verification of microprocessor-based designs for which previous approaches are shown to be inadequate. It introduces the concept of sequential path tracing -tracing paths through both space and time -that forms the basis of the mtv tool. mtv has the following novel features: unlike previous approaches, it considers sequential behavior together with timing and handles sequential sensitizability and multi-cycle paths automatically; it does not require a predefined clock schedule and can handle circuits with conditional or gated clocks, multiple unrelated clocks, asynchronous set/reset, and power-up initialization; it generates symbolic constraints between timing attributes of components that can be efficiently re-used for small circuit changes or by a synthesis/optimization tool; symbolic constraints also enable common ambiguity removal.Experimental results demonstrate that mtv takes only a few CPU minutes to generate symbolic constraints for each of several microprocessor-based designs.

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