Practical applications of an efficient time separation of events algorithm

Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gate-level circuits. It also presents an algorithm based on partially ordered sets to make the state-space exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gate-level timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance.

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“…There have been two nice proofs of STARI's correctness [34], [36], but they have been on abstract models. Fig.…”

Section: A Asynchronous Circuit Verificationmentioning

confidence: 99%

Timed circuit verification using TEL structures

Belluomini

Myers

Hofstee

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…There have been two nice proofs of STARI's correctness [21,23], but they have been on abstract models. In [22], the authors state that COSPAN which uses the unit-cube (or region) technique for timing verification [24] ran out of memory attempting to verify a 3 stage gate-level version of STARI on a machine with 1 GB of memory.…”

Section: Ack(1)precedes X(0)t-and X(0)f-) and (2) A New Data Value mentioning

confidence: 99%

Verification of timed systems using POSETs

Belluomini¹,

Myers

1998

Computer Aided Verification

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This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state space by considering partially ordered sets of events rather than linear sequences. This approach avoids the explosion of timed states typical of highly concurrent systems by dramatically reducing the ratio of timed states to untimed states in a system. A general class of timed systems which include both event and level causality can be specified and verified. This algorithm is applied to several recent timed benchmarks showing orders of magnitude improvement in runtime and memory usage.

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“…Hulgaard et al observed in [6] that the isochronic fork assumption is too strong, and can be relaxed as follows: the circuit will function correctly as long as forked transitions that do not have a successor transition in the STG (and thus are not acknowledged) occur before they are used later in the execution of the circuit. This can be accomplished by adding causal ∆ i constraints from such fork transitions to the appropriate transitions.…”

Section: F Examplementioning

confidence: 99%

“…5 which was reported in [6]. The D-element synchronizes two components that use handshakes to communicate.…”

Section: F Examplementioning

confidence: 99%

Assessing the feasibility of interface designs before their implementation

Escalante

Dimopoulos

1995

Proceedings of the 1995 Conference on Asia Pacific Design Automation (CD-ROM) - ASP-DAC '95

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-During the design of microprocessor-based systems, once the system architecture has been decided and the major components (processors, memories, IO devices) have been selected from a component library, it is necessary to design interface logic to integrate the system. Such an interface design can be carried out based on the protocols used by the components. This paper addresses the problem of determining the feasibility of a design prior to synthesis. A design is called feasible if it achieves the desired functionality and satisfies the given environmental constraints. Because timing is an important aspect of a correct design, protocols are described using timed signal transition graphs, an interpreted Petri net. It is shown here that the feasibility of designs whose corresponding behavior is periodic can be studied using a technique called timing analysis for synthesis. I. INTRODUCTIONAs the complexity of hardware systems increases, techniques that facilitate their design and verification are invaluable to hardware designers. The DAME project [3] aims to automate the design of microprocessor-based systems. DAME's main strength is its finer component representation down to the interfacing protocol level. DAME follows a top/down design process in which first a system architecture is decided, then the major components (processors, memories, and IO devices) are selected from a library according to system-level design constraints such as type of application, throughput, cost, etc. The next step is system integration, during which DAME designs the necessary glue logic to interconnect the major components that comprise the system. In this paper we address the problem of verifying that such an interface design is feasible before synthesis is attempted, i.e. that the interface generates the necessary events at the expected times to accomplish the intended inter-component communication.Thus it is possible to avoid the design-synthesis-verification cycle: a design is first synthesized, then checked against its specification, and if verification fails the process is repeated.In order to be able to describe the protocols used by offthe-shelf microprocessor components we have developed a representation of timed behaviors based on a Petri net model which allows us to reason about circuit delays and environmental timing constraints.Our model is suitable for symbolic timing analysis that finds the tightest bounds on the unknown interface path delays before the actual circuit is implemented [4]. Delay-insensitivity [1] is a special case of circuit design in which timing constraints are satisfied by any implementation regardless of the circuit delays. Synchronous and partial handshake protocols can be considered as variations of the full handshake with missing event precedence links, requiring less control cir-

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Practical applications of an efficient time separation of events algorithm

Cited by 11 publications

References 4 publications

Timed circuit verification using TEL structures

Timed circuit verification using TEL structures

Verification of timed systems using POSETs

Assessing the feasibility of interface designs before their implementation

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