Timed circuit verification using TEL structures

Belluomini, Wendy; Myers, Chris J.; Hofstee, H. Peter

doi:10.1109/43.905681

Cited by 13 publications

(6 citation statements)

References 43 publications

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“…This chapter discusses several model checking tools for hybrid systems and AMS circuit verification. Next, this chapter introduces a set of algorithms to perform reachability analysis of constant rate LHPNs using DBMs based upon a reachability analysis algorithm for analyzing timed systems [25,26]. This chapter includes an error trace generation method for LHPNs and concludes with an example of reachability analysis on the motivating example.…”

Section: Warping Dbmsmentioning

confidence: 99%

“…If a failure trace has been fired or deadlock is found a pair of error traces are created and the current state space and error traces are returned (lines 16-18 and 20-22, respectively). If the state set has been seen before, an edge is added to the graph, the stack is popped and the loop continues (lines [23][24][25][26]. If the stack is empty, the reachable state space has been found and is returned with an empty error trace (lines 27-28).…”

Section: Reachability Analysis Of Lhpns Using Dbmsmentioning

confidence: 99%

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Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Little¹,

Walter

Myers

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Analog circuit design is traditionally done by expert designers in an ad hoc manner heavily dependent on simulation. This methodology has worked successfully for many years, but process variation and design complexity are prompting designers to explore new techniques. Formal methods are being used successfully to aid in the complex validation problem for digital circuits. This dissertation presents formal methods for analog and mixed-signal (AMS) circuits. This dissertation describes the development of a formal model, labeled hybrid Petri nets (LHPNs), appropriate for the modeling and verification of AMS circuits. An LHPN is a Petri net variant capable of modeling both continuous and discrete quantities. Creating an LHPN model of an AMS circuit by hand is a complicated and error prone exercise that requires expert knowledge. This is unacceptable for practical adoption of the LHPN model and its associated analysis methods. For this reason, this dissertation introduces an automatic LHPN model generation method. The method uses a set of simulation traces and a desired system property to generate an LHPN modeling the behavior of the simulation traces. The model generator can also be used to generate abstract Verilog-AMS or VHDL-AMS models suitable for use in system-level simulations. Formal verification of a property over the entire state space of an LHPN model is complicated by the infinite state of the model. For this reason, the infinite states of the model are grouped into potentially finite groups of equivalent states for verification. Difference bound matrices (DBMs), a restricted form of convex polygons, are used to represent these equivalent classes of infinite states. Reachability analysis using DBMs is very efficient at the cost of exactness. This dissertation presents algorithms for conservative state space analysis and verification of LHPNs.Finally, these methods are demonstrated on several case studies of AMS circuits from both academia and industry. The formal verification methods demonstrate the ability to find bugs missed by standard simulations. The abstract modeling methods show the promise of using automatically generated abstract models by demonstrating up to 40x speedup for some examples.

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Section: Warping Dbmsmentioning

confidence: 99%

Section: Reachability Analysis Of Lhpns Using Dbmsmentioning

confidence: 99%

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Little¹,

Walter

Myers

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Our analysis method uses zones defined using difference bound matrices (DBMs) [7] to represent the continuous portion of the state space. Our methodology is based upon one for analyzing timed systems [2,3] with extensions necessary to deal with continuous quantities changing at variable rates. The state sets are represented with the tuple ψ = M, S, Q, R, I, Z where:…”

Section: Analysis Of Lhpnsmentioning

confidence: 99%

Verification of analog/mixed-signal circuits using labeled hybrid petri nets

Little

Seegmiller

Walter

et al. 2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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System on a chip design results in the integration of digital, analog, and mixed-signal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDL-AMS to LHPNs. To support formal verification, this paper presents an efficient zone-based state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixed-signal circuit examples.

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“…this kind of timing constraints is less restrictive than metric timing constraints 1 [6,7] and easier to validate than relative timing constraints 2 [19,21]. This additional freedom can be used to select more aggressive delays for larger performance gains.…”

Section: Introductionmentioning

confidence: 97%

Verification of Concurrent Systems with Parametric Delays Using Octahedra

Clarisó

Cortadella

Fifth International Conference on Application of Concurrency to System Design (ACSD'05)

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A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters sufficient to guarantee the property. The main contribution is an innovative representation of the parametric timed state space based on bit-vectors. Experimental results from the domain of timed circuits show that this representation improves both CPU time and memory usage with respect to another parametric approach, convex polyhedra.

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Timed circuit verification using TEL structures

Cited by 13 publications

References 43 publications

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Verification of analog/mixed-signal circuits using labeled hybrid petri nets

Verification of Concurrent Systems with Parametric Delays Using Octahedra

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