Tien-Yu Lo scite author profile

This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages. Index Terms-Digital CMOS, flip-flop, low power, low voltage, VLSI.

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Tien-Yu Lo

An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS

A Wide Tuning Range G$ _{\rm m}$–C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers

A 1-V 50-MHz Pseudodifferential OTA With Compensation of the Mobility Reduction

A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops

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