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The success of the model-based infrared reflectrometry (MBIR) technique relies heavily on accurate modeling and fast calculation of the infrared metrology process, which continues to be a challenge, especially for three-dimensional (3D) trench structures. In this paper, we present a simplified formulation for effective medium approximation (EMA), determined by a fitting-based method for the modeling of 3D trench structures. Intensive investigations have been performed with an emphasis on the generality of the fitting-determined (FD)-EMA formulation in terms of trench depth, trench pitch, and incidence angle so that its application is not limited to a particular configuration. Simulations conducted on a taper trench structure have further verified the proposed FD-EMA and demonstrated that the MBIR metrology with the FD-EMA-based model achieves an accuracy one order higher than that of the conventional zeroth-order EMA-based model.

Through silicon via is a promising technology that has benefits of high density, excellent performance and heterogeneous integration for 3D stacked devices, where blind silicon via plating in via first and via middle approaches is widely used. However, using conventional damascene copper plating technology to achieve high quality copper filling of blind vias is very difficult. In this paper, we demonstrate a novel approach for realizing bottom–up copper filling of blind silicon vias. Electroplating of the blind vias is carried out by using a titanium barrier layer, instead of the traditional copper seed layer, as the conductive medium. A vacuum process is introduced to push photoresist completely into the blind vias. By controlling the exposure and development processes, the photoresist at the top and middle of the vias is removed while that at the bottom it is retained for protecting the seed layer. After etching the exposed seed layer, we obtain a unique metal layer structure in which the copper seed layer is reserved at the via bottom, facilitating spontaneous bottom–up plating. Using this approach, we realize high quality copper filling of blind silicon vias of 30 µm in diameter and 120 µm in depth, which will be of noteworthy benefit in 3D electronic packaging.

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Nanostructures have attracted great interest in interconnect applications. Herein, we present a novel low temperature, templateless method for directly preparing Cu nanowires through a hydrogen thermal decompositionreduction route of Cu(OH) 2 → CuO → Cu. The thermal treatments are performed at relatively low temperatures of 180 °C-200 °C to meet the low thermal budget in the semiconductor industry. Cu(OH) 2 nanowires are completely transformed into Cu nanowires and the morphologies of the nanowires are successfully preserved without shrinkage of volume and size. Sintering of Cu nanowires occurs at a low temperature of 400 °C in Ar ambient and 350 °C in H 2 ambient, respectively. Based on this phenomenon, we innovatively apply the assynthesized Cu nanowires in Cu-Cu bonding at 150 °C-400 °C. The bonded samples exhibit high shear strengths where Cu nanowires have transformed into Cu nanoparticles, mainly attributed to the enhanced atom diffusion with the existence of nanowires. The present work demonstrates the feasibility of hydrogen thermal reductive Cu nanowires in low temperature Cu-Cu bonding.

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