This paper reports on a method for the investigation of mechanical stress on MEMS sensor and actuator structures due to packaging processes. A silicon test chip is developed and manufactured to validate the simulation results. Finite element analysis (FEA) is used to optimize the geometric parameters and to find a stress sensitive sensor geometry. A diaphragm structure is used as mechanical amplifier for bulk induced stresses during the packaging process. Piezo resistive solid state resistors are doped into the surface of the chip to measure the stress in the diaphragms and at the contact pads being most significant locations for analysis. A high precision ohmmeter was used to measure the resistance prior and past the packaging process. The captured data allows for computation of the resulting stress loads in magnitude. Therefore, a stress evaluation of different packaging technologies is conducted and the impact of the packaging process on reliability can be estimated immediately.
If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -The purpose of this paper is to present a new multilayer process for three-dimensional molded interconnect devices (3D-MIDs) that allows the assembly of modern area array packaged semiconductors. Design/methodology/approach -A new 3D-MID multilayer process based on local overmolding is developed. To investigate this new process, a 3D demonstrator is designed, simulated and fabricated. Various technologies such as injection molding, maskless laser assisted electroless metallization, overmolding and laser via drilling are used. Findings -Using the new 3D-MID multilayer process a 3D demonstrator with three metallization layers is fabricated. Injection molding simulation is utilized to ensure a feasible demonstrator design. It is shown that a surface laser treatment improves layer-to-layer adhesion during the process. Shear and pull tests prove the adhesion promotion. The 3D fine-pitch-metallization is done down to 60 mm track width. Via resistance is measured by four terminal sensing in agreement with previous results. Design rules for process compatible vias are introduced. The fabricated demonstrator is suitable for flip-chip-based area array packaged semiconductors.Research limitations/implications -A proof of concept is given by the fabricated demonstrator. Further, work should include reliability tests of the multilayer structures and improvement of individual process steps. Originality/value -The paper describes a new multilayer process for 3D-MIDs. It overcomes existing restrictions regarding the electrical routing on 3D-MID surfaces. The compatibility of area array packaged semiconductors with a high-inputs/outputs count and the 3D-MID technology is improved.
The implementation of fluidic functions in 3D-MID (three dimensional molded interconnect devices) allows to create a new field of applications and enhanced system solutions. We report about the capabilities of MID for the packaging of chip modules with microfluidic functions. A mechanically stable and leak tight fluidic connection is needed between the microfluidic chip and the environment. For this purpose a fluidic interposer is fabricated by the LDS-process (laser direct structuring) and includes a metallization for electrical signals and channel structures for fluidic features. The presented interposer enables the transformation of fluidic ports from the macro-to the micro scale. To characterize the device, a microfluidic test chip made of silicon and glass (Borofloat ® ) has been fabricated and mounted on the fluidic interposer by a flip-chip vapor phase process. Finally the potential of the system is shown by testing maximum pressurization and fluidic sealing.
The permanent miniaturization of automotive, medical and consumer products requires alternative packaging solutions. So far most electronic products are circuit boards mounted in a separate body. An upcoming alternative are moulded interconnect devices (3D-MID). They combine the substrate function for interconnects and the housing function. To ensure a high integration density it is necessary to apply fine pitch metallizations to the polymer devices. The purpose of this research concerns a novel process design in order to fabricate fine pitch metallizations for MID. A commercial catalytic material is applicated by a selective aerosol deposition process on a polymer � ubstrate. Subsequently, electro less copper plating Implements the metallization. The combination of 3D injection moulded components and this additive metallization process enables the fabrication of fine-pitch structures. The electrical and mechanical characteristics are excellent. In contrast to popular laser structuring a wide range of polymer materials can be used to produce 3-dimensional interconnect devices. The applicability of the novel catalytic aerosol deposition process is verified by investigation of deposition characteristics for various polymer materials. The smallest line width and the resistivity are investigated. Basic SMD circuits are assembled by vapour phase soldering. The shear forces to remove these SMDs are recorded to determine the metallization performance. Finally, these circuit samples are tested for reliability by performing temperature cycles.
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