A silicon test chip for the thermomechanical analysis of MEMS packagings

Abstract

This paper reports on a method for the investigation of mechanical stress on MEMS sensor and actuator structures due to packaging processes. A silicon test chip is developed and manufactured to validate the simulation results. Finite element analysis (FEA) is used to optimize the geometric parameters and to find a stress sensitive sensor geometry. A diaphragm structure is used as mechanical amplifier for bulk induced stresses during the packaging process. Piezo resistive solid state resistors are doped into the surface of the chip to measure the stress in the diaphragms and at the contact pads being most significant locations for analysis. A high precision ohmmeter was used to measure the resistance prior and past the packaging process. The captured data allows for computation of the resulting stress loads in magnitude. Therefore, a stress evaluation of different packaging technologies is conducted and the impact of the packaging process on reliability can be estimated immediately.

Stress analysis during assembly and packaging

“…The change in drain current within these orthogonal Si-MOSFETs due to applied mechanical stress is described by the theory of piezoresistivity of silicon [4,5]  …”

“…Starting with pioneering work at Infineon [1,2] several European research institutes now offer CMOS stress measurement facilities, e.g. university of Magdeburg [3,4], ETH Zurich [5], IMTEK at university of Freiburg [6] and Fraunhofer IZM [8].…”

Reliability Testing and Stress Measurement of QFN Packages Encapsulated by an Open-Ended Microwave Curing System

“…The calculation of the components can be performed with an accuracy of 13%, while shear stress and normal stress differences can be calculated with an accuracy down to 4.5% and 1.2%, respectively [19]. These accuracies apply as long as the stress component σzz normal to the chip surface is negligible (< 10 MPa) or is known and the temperature is measured correctly [20]. The measurement accuracy further depends on the integration time during measurement [21].…”

“…This section of the article attempts to verify experimentally whether this is the case. Many versions of stress-measurement chips have been developed within the last decade in order to measure residual stresses during curing and subsequently optimise the heating process [15][16][17][18][19][20][21]. The chip used in this study was developed by Robert Bosch GmbH as part of the BMBF-funded project iForceSens [19].…”

“…The test chip itself was fabricated using CMOS technology and contains orthogonal current mirrors sensitive to stress [19]. For this chip, an external mechanical load causes an asymmetry of the current mirrors [20]. The change in the drain current within these orthogonal Si-MOSFETs is described by the theory of piezoresistivity as applied on silicon:…”