CdTe photovoltaics has achieved one of the lowest levelized costs of electricity among all energy sources. However, for decades, carrier lifetimes have been inferior to those of other prevalent solar cell materials. This quality has inhibited common methods to improve solar cell efficiency such as back‐surface fields, electron reflectors, or bifacial solar cells. In this work, a significant increase in carrier lifetime to values exceeding 200 ns in fully functional CdTe solar cells is demonstrated. The increased lifetime is achieved by large CdSeTe grains at the absorber/emitter interface, intragrain passivation in the absorber layer, and chemical passivation by forming nanoscale oxidized tellurium species at the transparent conducting oxide interface. The carrier lifetime is correlated to the open‐circuit voltage and enables paths for back‐surface manipulation and novel cell architectures to further improve CdTe photovoltaic performance.
Polycrystalline thin-film solar cells are attractive for low-cost photovoltaics, but their efficiencies are hindered by material quality issues. State-of-the-art CdTe solar cells use CdCl2 annealing treatments whose effects are still being discovered at a fundamental level. Here, a series of CdTe samples with different annealing temperatures is investigated with high-resolution hyperspectral cathodoluminescence mapping measured at both room-and low-temperature on the same microscopic areas. A statistical analysis over a large number of grains is combined with a local analysis at grain boundaries. The results elucidate the dynamic interplay between grain boundary and intragrain defect passivation and formation, in the midst of grain growth. The CdCl2 annealing initially contributes to an increase of the grain size and the passivation of both grain boundaries and grain interiors, increasing the overall luminescence and diffusion length. For higher annealing temperatures, a further increase of grain size is counterbalanced by the rise of bulk defects. The results illustrate the tradeoffs that lead to an optimal annealing temperature, as well as new methods for understanding defect passivation and creation in thin film solar cells.
Cathodoluminescence mapping is used as a contactless method to probe the electron concentration gradient of Te-doped GaAs nanowires. The room temperature and low temperature (10 K) cathodoluminescence analysis method previously developed for GaAs:Si is first validated on five GaAs:Te thin film samples, before extending it to the two GaAs:Te NW samples. We evidence an electron concentration gradient ranging from below 1 x 1018 cm-3 to 3.3 x 1018 cm-3 along the axis of a GaAs:Te nanowire grown at 640 °C, and a homogeneous electron concentration of around 6 - 8 x 1017 cm-3 along the axis of a GaAs:Te nanowire grown at 620 °C. The differences in the electron concentration levels and gradients between the two nanowires is attributed to different Te incorporation efficiencies by vapor-solid and vapor-liquid-solid processes.
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