Abstract

No abstract

Performance is nowadays becoming a crucial issue for mobile apps, as they are often implementing computationalintensive features, are being used for mission-critical tasks, and, last but not least, a pleasant user experience often is a key factor to determine the success of an app. This paper reports a study aimed at preliminarily investigating to what extent developers take care of performance issues in their commits, and explicitly document that. The study has been conducted on commits of 2,443 open source Android apps, of which 180 turned out to contain a total of 457 documented performance problems. We classified performance-related commits using a card sorting approach, and found that the most predominant kinds of performance-related changes include GUI-related changes, fixing code smells, network-related code, and memory management.

Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.

In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V,