FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology

Thind, Vandana; Pandey, Bishwajeet; Kalia, Kartik; Hussain, Dil Muhammad Akbar; Das, Teerath; Kumar, Tanesh

doi:10.14257/ijseia.2016.10.6.07

Cited by 10 publications

(9 citation statements)

References 12 publications

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“…multiplier based on HSTL IO Standard [6], DES Algorithm Design [7] and Arithmetic Logic Unit Design on 28nm FPGA using SSTL [8] .…”

Section: A Cmos-based Tactile Sensor For Continuous Blood Pressure Momentioning

confidence: 99%

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Sharma¹

2017

GJECS

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Abstract-Out of control blood pressure whether it is low or high can be dangerous and major cause of heart disease. The people suffering from blood pressure problems are increasing day by day. The main objective of this paper is to make a wrist band which can monitor the blood pressure of our body at any time. The approach is to make it consume low power for its operation. Technique applied for doing same is capacitance scaling using Field Programmable gate Array using Xilinx software. The power consumption at frequency 0.2GHz, 1GHz, 2GHz, 20GHz and 200GHz is calculated for Low PowerVirtex6 FPGA.

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“…multiplier based on HSTL IO Standard [6], DES Algorithm Design [7] and Arithmetic Logic Unit Design on 28nm FPGA using SSTL [8] .…”

Section: A Cmos-based Tactile Sensor For Continuous Blood Pressure Momentioning

confidence: 99%

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Sharma¹

2017

GJECS

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“…The traditional symmetric/asymmetric algorithms are used for the data security such as DES [27][28][29], triple DES [30], elliptic curve cryptography (ECC) [31][32][33][34], Rivest-Shamir-Adleman (RSA) [35], etc. In these algorithms, ECC and RSA are well known asymmetrickey-cryptography that use public keys for encryption/decryption processes.…”

Section: Introductionmentioning

confidence: 99%

“…This work uses composite field arithmetic structure both SubBytes and InvSubBytes transformations with the speed efficient subpiplining structure. Earlier approach of implementing CFA is to decompose GF (28) as GF(((22)2)2). Where in this work GF (28) is decomposed as GF((24)2).…”

Section: Introductionmentioning

confidence: 99%

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A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Kumar

Reddy²,

Rinaldi

et al. 2021

Electronics

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Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

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“…High energy consumption is one of the major challenges to be solved in designing the NUMA multicore systems and other systems [1,25]. The memory access time imbalance among cores in different nodes is one source of energy inefficiency.…”

Section: Introductionmentioning

confidence: 99%

Reducing Energy Cost of Multi-Threaded Programs on NUMA Architectures

Fang¹

2018

IJPE

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Many recent data center servers are built with NUMA (Non-Uniform Memory Access) characteristics. Accessing remote memory generally takes longer time than accessing local memory. There are a lot of research works that discuss the performance improvement of NUMA multi-core systems. However, rare research work considers reducing the energy cost of NUMA multi-core systems. This work studies reducing energy cost of multi-threaded programs on NUMA architectures using DVFS (Dynamic Voltage and Frequency Scaling) adjustment strategy. We consider three factors of the multi-threaded programs which influence the energy saved by our DVFS adjustment strategy. These three factors are: (1) the memory access intensity of parallel programs; (2) the proportion of remote memory access; (3) the ratio between remote and local memory access latency. In addition, we propose two DVFS adjustment strategies to save the energy cost of multi-threaded programs. The energy-saving effect of these two DVFS adjustment strategies is influenced by these three factors. Two DVFS adjustment strategies can save maximally 20% and 39.2% of total energy when considering one factor and 33.3%, 48.1% of total energy when considering two factors, respectively.

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FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology

Cited by 10 publications

References 12 publications

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

Wrist Band Design using Low Power Virtex6 FPGA for Monitoring Blood Pressure

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Reducing Energy Cost of Multi-Threaded Programs on NUMA Architectures

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